Role & responsibilities Preferred candidate profile HI , we do have openings for Physical design Director at Hyderabad Product company JD: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 20+ years Hardware Engineering experience or related work experience. 17+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Thanks & Regards, Sowjanya. S Sr. Technical Recruiter Cambio Consulting | Hyderabad. Email: sowjanya@cambio.co.in Phone: 8978937319
Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.
Job Description: . Required Skills and Experience: Bachelor or Masters degree in Electrical or Computer Engineering 4-7 years of experience in developing timing & power models (NLDM, CCS, etc.) for standard cell, I/O and custom circuits preferably in 12nm and below nodes Hands on experience with running PrimeTime, extracting timing data for custom PnR blocks In depth knowledge of electrical engineering fundamentals including CMOS device operation and characteristics, including understanding of advancing modeling techniques Hands on experience with simulation using HSPICE, Hsim or Finesim Experience with scripting tools such as Python/Perl/Shell etc. Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence) Commitment (responsible, responsive, committed to winning) Work quality ("do it right the first time," attention to detail, good documentation) Strong analytical, problem-solving skills and excellent communication skills Requirements/Qualifications: Exposure to Physical verification using LVS and LPE tools (Synopsys Hercules or Mentor Graphics Calibre and StarRC-XT) Exposure to Static Timing analysis at gate level or transistor level with tools such as PrimeTime or NanoTime Exposure to Standard cell characterization tools such as SiliconSmart Working knowledge of SOC and/or FPGA Architectures Knowledge of FPGA design synthesis and routing associated with Microchip (Libero), Xilinx (ISE), or Altera (Quartus) tools Working knowledge of ASIC/FPGA design flows with a focus on timing and power analysis tools.
Role & responsibilities Preferred candidate profile Bachelor's or Master's degree in Computer Science, Electrical Engineering Extensive experience in embedded software development, with a strong emphasis on C programming. Deep expertise in Linux kernel development, including device drivers, kernel modules, and system calls. Proven experience in hardware bring-up and debugging embedded systems. Strong understanding of networking concepts and protocols (TCP/IP, Ethernet, Wi-Fi, etc.) and their implementation in embedded Linux Familiarity with various embedded communication protocols (I2C, SPI, UART, USB, PCIe, etc.).BIOS/UEFI: Expertise in UEFI bootloaders, storage protocols (SATA, NVMe,AHCI), and x86 architecture. Familiarity with high-speed SerDes, Ethernet/PCIe PHYs, optical modules, and Layer 1 (L1) hardware components Proven experience in hardware bring-up and debugging embedded systems. Familiarity with various embedded communication protocols (I2C, SPI, UART, USB, PCIe, etc.). Strong understanding of ARM and MIPS processor architectures and associated hardware interfaces. Proficiency with debugging tools (e.g., GDB, JTAG, oscilloscopes, logic analyzers). Strong leadership, communication, and problem-solving skills.
Hello !!! Hiring for the SW QA Engineer for Product MNC'S in Chennai. Please find the JD below. Dev-test, Testing and automation experience in networking Hand-on experience with various test automation framework (Robot, Python ) Demonstrated experience in testing networking and security products Experience in platform testing which includes Traffic testing, Optics/Cables , RFC2544 Latency and throughput testing Experience in working with Hardware components qualification and Broadcom/Cavium/Intel chipset Interested candidates please your updated CV to sravanthiparsha@cambio.co.in
Hello !!! Hiring for AI Switching Architect in Product MNC's @ Hyderabad & Bangalore Please find the JD below. 15+ years of hands-on experience in Hyperscale/AI Networking Infrastructure, IP routing protocols (e.g., BGP, OSPF, IS-IS), and Ethernet switching technologies for AI Networking like UALink, Ultra Ethernet. This includes architecting and deploying large-scale networks for global service providers and cloud operators Interested candidates please share your updated CV to sravanthiparsha@cambio.co.in
Job Title: Design Verification Engineer (5+ Years Experience) Location: Bengaluru & Hyderabad, India Company: Services Company --- About the Role: We are looking for a highly experienced Design Verification Engineer with strong expertise in PCIe or DDR protocols to join our dynamic hardware engineering team in Bengaluru. The ideal candidate will have a proven background in developing and executing verification plans for complex IPs and SoCs, along with a deep understanding of verification methodologies and tools. --- Key Responsibilities: Develop and execute comprehensive verification plans for IP and SoC-level designs. Create and maintain testbenches using SystemVerilog and UVM methodology. Define and implement constrained random and directed test cases to ensure functional coverage. Work closely with design, architecture, and validation teams to identify and resolve design and verification issues. Perform coverage analysis, debug failures, and drive closure on coverage metrics. Contribute to automation and regression infrastructure improvements. Deliver high-quality verification results on schedule with minimal supervision. --- Mandatory Skills: Hands-on experience in PCIe or DDR (any one is mandatory) Expertise in SystemVerilog and UVM methodology Strong understanding of digital design concepts, SoC/IP architecture, and bus protocols. Experience with simulation, debugging, and coverage tools (VCS, QuestaSim, Verdi, etc.) Solid experience in testbench development and functional coverage closure. --- Preferred Skills: Exposure to AMBA (AXI/AHB/APB), Ethernet, or other high-speed interfaces. Scripting knowledge (Python, Perl, or Shell). Familiarity with formal verification and assertion-based verification (SVA). Experience working with cross-functional global teams. --- Qualification: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Minimum 5 years of relevant experience in design verification.
Hi We have Openings for Sr. Staff SW QA Engineer - Platforms - India - Hybrid with Product company in Chennai Please share your CV on aradhana@cambio.coin Regards Aradhana