500 System Verilog Jobs - Page 11

Location : Company Name: Mirafra Technologies Positionskill set : PCIE Experts (Design Verification) Location: Hyderabad Experience: 6 to 12 Years Open Positions: 8 Notice Period: 0 to 40 Days Preferred Job Type: Full-Time Selection Type: All offers are client selection-based Location: Hyderabad/Bangalore Job Description: Mirafra is hiring experienced PCIE Verification Engineers for exciting opportunities with leading semiconductor clients in Hyderabad. If you're passionate about solving complex verification challenges, we want to hear from you! Key Responsibilities: In-depth understanding of verification flows and methodologies Hands-on experience with complex testbenches/models in Verilog, SystemVerilog, or SystemC Strong debug skills and a problem-solving mindset Functional and SoC-level verification, including emulation exposure Proficiency in SystemVerilog, PLI/DPI interfaces, C/C++, Perl/Shell scripting , and assembly language Experience with OVM/UVM methodologies Ability to work collaboratively in a team environment Good communication and interpersonal skills Preferred Skills: Background in x86 or ARM architecture-based SoCs Experience in SoC/IP performance verification is a plus Apply Now: If you meet the above requirements and are available within 0 to 40 days, send your resume to: [swarnamanjari@mirafra.com] or Click the apply button

Responsibilities: SoC integration/scenario/performance verification including CHI, DDRx/LPDDRx, and AI accelerator blocks in RTL. Develop test plans, SystemVerilog/Verilog testbenches, and C-based embedded tests. Collaborate with cross-functional teams architecture, design, performance, silicon validation, FPGA, and board teams. Plan, track and report verification tasks to management. Skills & Experience Required: Strong knowledge of Verilog/SystemVerilog HDL. Hands-on experience in SoC verification using embedded C/C++/assembly (ARM preferred). Experience in UVM/OVM, emulation, formal verification, UPF/Power-aware verification. Expertise in GLS, DFT/DFD, CDC (Clock Domain Crossing). Familiar with ARM SoC boot flows, cache coherency, SoC verification flow & strategy. Scripting experience in Python, Perl, Tcl, Shell. Excellent debugging and problem-solving skills.

Role Greetings from Sivaltech!! Hope you are doing great!!!! We have an exciting job opportunity for Lead Design Verification Engineer in Sivaltech for both Bangalore and Hyderabad locations. Please find below the detailed Job Description and Company Profile as well. • Working experience in IP / SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Sivaltech is a product engineering company with expertise in silicon design and software development. Our head office is in Milpitas, California, U.S.A. with branches in India at Bengaluru and Hyderabad& responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Principal Software Engineer Location: Noida Job Responsibilities: The role s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Experience: 10-15 Years Required Skills The successful candidate will possess the following combination of education and experience: Proficient in C/C++ Excellent programming and software engineering skills Experience with UNIX and/or LINUX platforms is preferred RTL knowledge - System Verilog, VHDL is preferred Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended Prior experience with timing analysis software development projects is highly recommended Data structure and algorithmic skills We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: We are looking for 14+ years of experience having the following skillset: Strong RTL design fundamentals using HDLs like VHDL/Verilog/System verilog Strong understanding of AMD (Xilinx) ultrascale, versal FPGAs architecture and use of vivado for FPGA place and route. Constraints definitions for FPGAs. Doing Static Timing Analysis. Familiarity with FPGA prototyping or emulation is a plus. Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Good written and verbal communication skills, should be a quick learner and a team player. We re doing work that matters. Help us solve what others can t.

Role & responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Preferred candidate profile Bachelors/ Masters degree or higher in EEE/ECE 4+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal Design Verification Engineer (India) India Company Background We areon a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. DDR5 Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-17years or MSEE/CE + 12-15 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

SILICON DESIGN ENGINEER 2 (AECG ASIC - SoC verification Engineer) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 2+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench under supervision from team lead. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification will be a plus Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 8 years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 Benefits offered are described: AMD benefits at a glance .

SMTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 14+years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 Benefits offered are described: AMD benefits at a glance .

Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working withmicrocontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog; Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

Must possess strong understanding on IP & SoC Verification with 5+ Years of exp. Must possess strong understanding in Verilog, SystemVerilog & C/C++. Must have strong debugging skills and able to narrow down issues in design.

Engineer must possess strong understanding on SoC Verification. Engineer must be having 5+ Years of Design Verification Understanding. Engineer must be fluent in Verilog, C/C++, SystemVerilog. Design Debugging skill is mandatory.

Engineer must possess strong understanding on IP & SoC Verification with 7+ Years of Design Verification Exp. Must possess string understanding on Verilog, SystemVerilog, C/C++. Must be able to debug the failure and able to narrow down the root cause.

We are seeking a highly motivated and skilled Design Verification Engineer with a strong background in UVM, SystemVerilog , and IP-level verification . The ideal candidate will be responsible for developing and executing robust testbenches, simulation, and debugging strategies to ensure first-time-right silicon. Key Responsibilities: Develop and maintain UVM-based verification environments for IP-level testbenches. Perform RTL and Gate-level simulation and debug functional issues. Define and execute comprehensive test plans to validate functional correctness. Integrate and verify AMBA bus protocols such as AHB and AXI. Develop and close assertions and functional coverage to meet verification completeness. Write reusable SystemVerilog assertions (SVA) and functional coverage models. Collaborate with design, architecture, and verification teams to debug and resolve complex issues. Utilize scripting languages ( Shell, Perl, Python ) to automate flows and enhance productivity. Participate in regular code reviews and contribute to verification process improvements. Communicate effectively across cross-functional teams and global engineering groups. Required Skills & Experience: Strong expertise in UVM and SystemVerilog for testbench development. Solid experience in RTL and gate-level simulation and debug . Hands-on experience in test planning, writing, and executing test cases . Good working knowledge of AHB/AXI bus protocols . Proficient in assertion-based verification and coverage development/closure . Working knowledge of C programming and scripting using Shell, Perl, or Python . Excellent communication, problem-solving, and team collaboration skills. Prior experience with IP-level DV and delivery is a must. Interested can share resume on Shubhanshi@incise.in

Responsibilities : - Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.- Participate in design reviews and contribute to the design process.- Stay abreast of the latest verification methodologies, tools, and industry trends.- Document and report on verification progress, issues, and risks. Qualifications : - 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).- Strong understanding of digital design fundamentals and verification methodologies.- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).- Good understanding of cache coherency protocols.- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.- Experience with UPF (Unified Power Format) and low-power simulation is a plus.- Excellent problem-solving, analytical, and debugging skills.- Strong communication and interpersonal skills.- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

Greeting with HCL Tech! We were looking somebody who is having experience in Design Verification Experience: 4 to 10 Years Location: Kochi Job Description: General verification expertise System Verilog. UVM Understanding of ARM processor based SOCs, AXI / AHB Good knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug) Strong hands on work experience of test development, simulation along with usage of popular EDA tools Good debug skills – Check that engineer has done reasonable amount of debug in past projects Has logical and methodical approach to debug issues /failures Has used standard tools for debugging, as applicable

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch. Maintain and improve existing DV environments. Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance. Support testing of design in emulation. Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications Bachelors Degree or equivalent experience in EE, CE, or other related field. 7+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying sophisticated blocks, clusters and top level for ASIC. Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Masters Degree in EE or CE with 5+ years of relevant work experience. Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Role: RTL Design Engineer Experience: 10+years Notice Period: Max 15days preferred Role Overview We are looking for a RTL Design Engineer? to deploy andsupport our front-end tools, to develop scripts to automate regression anddebug flows, and to work along with our design, implementation and verificationteams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree or equivalent experience / Master's Degree or equivalent experience in Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, Qualifications: Minimum Qualifications: BE/Btech/MTech with 6 Plus years of experience Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware and other tests as a guide Experienced with the architecture, microarchitecture and Power Management flows and debugging failures to the root cause Develop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models Develop tools and methods to streamline validation of PM flows, PM HW/FW interactions, and SOC level validation to deliver highest quality design in shortest time possible. Job Type: Experienced Hire