2 - 4 years

20 - 25 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies
  • Create and maintain verification plans, focusing on functional and code coverage metrics to ensure design quality
  • Perform black box testing for complex designs to identify potential issues early in the verification cycle
  • Debug verification issues using advanced troubleshooting techniques and provide effective solutions
  • Collaborate with design teams to align verification strategies with project requirements
  • Create and maintain detailed documentation for verification processes and results
  • Participate in design reviews and provide verification insights to improve overall product quality
  • Apply scripting skills to automate verification tasks and improve efficiency

Must Have Skills
  • SystemVerilog and UVM : Proficiency in developing and maintaining verification environments using SystemVerilog and Universal Verification Methodology for complex designs
  • Test Bench Development : Ability to develop comprehensive test benches for mixed-signal product verification, focusing on coverage-driven methodologies
  • Scripting : Capability to create and implement automation scripts using Python, Perl, or TCL to enhance verification workflows
  • Verilog RTL : Strong understanding of Register Transfer Level design concepts and their application in verification
  • EDA Tools : Experience with electronic design automation tools and simulators for effective design verification
  • Debugging : Demonstrated ability to analyze and resolve moderately complex verification issues with limited supervision
  • Communication Protocols : Working knowledge of standard interfaces such as I2C, SPI, and UART, and their verification requirement

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