500 System Verilog Jobs - Page 15

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Experience 2 to 4 years of experience Hands on experience with FPGA design toolsSynplify, Vivado, XILINX ISE, Work experience in FPGA based design implementation . FPGA RTL coding (Verilog/VHDL/System Verilog), FPGA constraint setup, verification, synthesis, Place and route and timing closure. Hands-on experience in WIFI/Ethernet/PCIe/USB/Multimedia/UFS/ARM CPU/DDR4/LPDDR5 emulation . Exposure/working experience in simulation acceleration emulation platforms like Veloce/PalladiumGate level simulation/emulation bring up Familiar with hardware schematics and Lab tools to debug. Work closely with RTL Design/Validation and Software teams for bug/issue debug, support and build bring up in emulation platform. Excellent teamwork, interpersonal and communication skills. Scripting/programming skill in C/C++, Tcl, Perl/Python/csh will be added advantage Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Title:DEVOPS- AWS Glue, KMS, ALB , ECS and Terraform/Terragrunt Experience5-10Years Location:Bangalore : DEVOPS, AWS, Glue, KMS, ALB , ECS, Terraform, Terragrunt

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 6 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg.I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Senior Engineer for our Build and Release Methodology Group catering to our pioneering SOCs. As the SOC development becomes more complex requiring packing of more and more IPs and the need for doing more SOCs increase, we need to have a scalable infrastructure to be able to complete SOC development in fastest as well as most efficient way possible. This requires an SOC Build and IP Release infrastructure that caters to and keeps up with these ever-increasing complexities. In this position, you will work first-hand on architecting and developing this methodology. If you have real passion for methodologies and automation solutions, you will fit in great! What youll be doing: Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner. Architect and implement core build flows so as to optimize build and make it simpler and efficient. Improve build, release, and integration tools and procedures. Identify and develop Checks to enforce the best practices for the Build and Release guidelines. Develop solutions to enable abstraction and compartmentalization for customer IPs. Identify difficulties and inefficiencies in the SOC implementation process and propose ideas to solve them. Support IP teams with Build and Release related issues. What we need to see: BS or MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience. 5+ years of industry experience as Build and Release Engineer, Build Automation, IP integration and related areas. Strong coding skills in Perl, Python, Makefile, Shell script, or other industry-standard scripting languages. Excellent analytical and problem-solving skills. Excellent interpersonal skills to work with multi-functional teams and collaborate with team members across sites and cultures to build consensus. Background in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus - Not must. Experience in synthesis and physical design is a plus - Not must. #LI-Hybrid

Senior Verification Engineer (hardware) We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators What We Offer : - Opportunity to work on cutting-edge semiconductor projects - Collaborative and innovative work environment - Professional growth and leadership opportunities

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows * Provide implementation flows support and issue debugging services to SOC design teams across various site * Develop and maintain 3rd party tool integration and product enhancement routines * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Experience 3 to 5 years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP IP HEXAGON DSP team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space Qualcomm is the largest fabless design company in the world, generating over $15 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software, and related services to nearly every mobile device maker and operator in the global wireless marketplace Job Responsibilities: Drive design verification of DSP Subsystem IP by working with a global DSP design team involving architecture, and power teams Implement and improve System Verilog Testbench Architecture Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals Hand-on simulations and debug Complete all required verification activities at IP level and insure high quality commercial success of our products Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification Responsible for power aware RTL simulation Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skillset/Experience: 5-8 years"™ experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation Expertise in UPF and PA RTL simulations Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object-Oriented Programming (OOP) concepts Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and (HDL) such as Verilog, SystemVerilog Experience in AMBA, AHB, AXI , APB and debug protocols Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI Experience is verification of Processor subsystems (ARM/DSP) is preferred Should have excellent inter-personal and communication skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years"™ experience in unit and subsystem level verification. Worked on coverage driven constraint random verification . Strong in System Verilog, UVM, Test planning Sound experience in testbench (stimulus, agent, monitor, checker) development. Worked in the verification having c based reference model inside the testbench Exposure in scripting(perl, Python).

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The candidate would be joining a team with deep expertise in designing IP for wireless sub-systems for market leading products. In this role, the candidate would be working on connectivity solutions for mobile phones, wearables, IOT and Mobile Infrastructure chips. The candidate would be a part of Bluetooth IP Design team and will be involved in IP and sub-system development. The role requires working on the latest technology nodes on all aspects of the VLSI development cyclearchitecture, micro architecture, RTL design and integration. Close interactions with system architecture, verification, SoC Design, Validation, Synthesis & PD teams are required for design convergence. Skills/Experience 2-6 years of experience in the design of complex ASICs Strong expertise in RTL coding of complex designs using Verilog/SV Exposure to low power design methodology and designs with multiple clock domains Strong debugging, analytical skills and strong communication skills, both verbal and written Hands-on experience in front-end design tools Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This is your role Siemens EDA SLS Bangalore group, a part of HAV Division of Siemens EDA, is looking for an engineer, who is primarily required to understand, design and implement solutions to improve the Codelink product, including new Processor support. This includes design and implementation of the functionality for the requirements in the domain, participation in design reviews and continuous improvement of product line that Siemens EDA has in this domain, interaction with co-workers and collaborators to improve the quality of the products, work with teams in different geographies and cultures. This role is based in Bangalore. But you'll also get to visit other locations in India and globe, so you'll need to go where this job takes you. In return, you'll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We are looking out for candidates with B.Tech/M.tech or equivalent experience in Computer Science or Electronics Engineering with shown experience & strong programming knowledge in C/C++ with strong object oriented design skills. We need someone who is good in algorithm and data-structure design skills with theoretical background in analysis of algorithms. Programming knowledge of Verilog/System Verilog is required. Adept at using one or more software development methodologies such as Agile. Problem Solving and Analysis Skills is required. Technical Skills required (Desirable) Experience in software development and debug is a plus! Experience in studying and understanding technical specifications. Knowledge of computer architecture concepts, especially processors. We are looking for someone with good understanding of configuration management tools such as git. Experience with defect tracking tools such as JIRA. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA #LI-HYBRID

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the Group: Join a dynamic and fast-evolving team that is building next-generation AI-based tools and agent systems for QuestaSim, flagship simulation software at Siemens EDA. We're focused on designing intelligent AI agents, optimizers, and copilots using modern AI/ML techniques. This is an R&D-heavy role with real-world applications, significant autonomy, and room to innovate. This role is based in Noida. But you'll also get to visit other locations in India and globe, so you'll need to go where this job takes you. In return, you'll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities: We are seeking a highly motivated and experienced software engineer with a strong background in AI/ML to join the QuestaSim (Simulation) R&D team at Siemens EDA. In this role, you will: Design and develop AI-powered agents using LLMs, LangChain, vector databases, and retrieval-augmented generation (RAG). Build intelligent systems that understand natural language queries and automate complex workflows. Integrate and experiment with ML pipelines, data-driven decision-making, and reinforcement learning for adaptive systems. Prototype and productize tools that leverage code understanding, profiling, and data analysis. Collaborate closely with AI researchers, UX designers, and backend teams to translate ideas into working products and robust features. Work on prompt engineering, few-shot learning, and tool use orchestration What We're Looking For: Must-Have: Hands-on experience with AI/ML frameworks (e.g., PyTorch, TensorFlow, Scikit-learn). We are looking for candidates with 2-4 years of proven experience. Strong working knowledge of LangChain, RAG pipelines, and vector stores. Strong understanding and experience in application of Deep Learning models like ANNs and transformers. Experience in developing AI agents or copilots that interface with tools or external APIs. Proficiency in Python; familiarity with software design patterns and clean code. Practical experience in data preprocessing, feature engineering, and model evaluation. Familiarity with LLMs (OpenAI, LLaMA, Claude, etc.) and prompt engineering best practices. Ability to identify AI use-cases, conceptualize solutions, and drive from prototype to production. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Good to Have : Background or interest in Digital Design, SystemVerilog, or EDA tools (can be learned on the job). Basic knowledge of compilers, parallelism, or profiling tools is a bonus. Why Join Us? Work on cutting-edge AI R&D projects with real product impact! Be part of a startup-like team within a global tech company. Opportunity to lead innovation, publish internally, and drive industry-first solutions. Competitive compensation, flexibility, and a collaborative culture. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid #DVT

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 12 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content. Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Logic Design Engineer to join our MIC IDC Design team in Bengaluru In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer, As a PE Logic Design Engineer, youll play a pivotal role in designing and implementing the worlds best Registered Clocking Driver (RCD) products In this full-time role, youll report directly to our Logic Design Manager Our MIC IDC is dedicated to leverage over three decades of high-performance memory expertise to deliver cutting-edge memory interface chipset solutions, enhancing memory bandwidth and capacity for data centers and client applications alike, and your contributions will be instrumental in RCD product development, Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the spec requirements and convert into a micro architecture specification, Realize the RTL design using Verilog/System Verilog, Works with verification teams in defining the test plan and reviews the test coverage, Does pre implementation design checks like lint, CDC, RDC, constraint validation, Works with physical design team in defining the design and timing constraints and driving implementation till timing closure, Interact with cross functional circuit teams for new product development Participate in Architecture level discussions to define the specifications, Post silicon validation support in bringing up parts, Qualifications Minimum 10 years of solid ASIC logic/Digital design expertise with bachelors degree or masters degree Strong digital design fundamentals, Strong hands on expertise in HDLs like Verilog/System Verilog, Experience with EDA tools for simulation, synthesis, and timing analysis and logic equivalence check, Knowledge of High speed protocols is plus, Strong scripting abilities using Perl/Tcl/python is a plus Strong written and verbal communication skills Able to break down technical concepts to a larger audience is desired, About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems, Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits, Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard, Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics, Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application, Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services, For more information about Rambus, visit rambus For additional information on life at Rambus and our current openings, check out rambus /careers/,

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP, You will: Put in dedicated effort to understand graphics concepts and enhance your verification expertise, Collaborate effectively within a team, demonstrating a willingness to learn and contribute, Take ownership of your tasks by planning, estimating, and tracking your progress, Assist in developing tests, sequences, checkers, scoreboards, and other components in UVM, About You Committed to making your customers, stakeholders and colleagues successful, youre an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say Youre curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard, You'll have: Strong expertise in Digital Circuits and Verilog, Proficient in SystemVerilog and UVM, with a strong desire to further enhance skills in these areas, You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures, Experience with broader verification technologies, including formal property-based verification (FPV), Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++, Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces, We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before, So come join us if you're wanting that something more Bring your talent, curiosity and expertise and well help you do the rest Youll be part of one of the worlds most exciting companies who are one of the leaders in semiconductor IP solutions, As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology, Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec ,

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP, You will: Put in dedicated effort to understand graphics concepts and enhance your verification expertise, Collaborate effectively within a team, demonstrating a willingness to learn and contribute, Take ownership of your tasks by planning, estimating, and tracking your progress, Assist in developing tests, sequences, checkers, scoreboards, and other components in UVM, About You Committed to making your customers, stakeholders and colleagues successful, youre an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say Youre curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard, You'll have: Strong expertise in Digital Circuits and Verilog, Proficient in SystemVerilog and UVM, with a strong desire to further enhance skills in these areas, You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures, Experience with broader verification technologies, including formal property-based verification (FPV), Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++, Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces, We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before, So come join us if you're wanting that something more Bring your talent, curiosity and expertise and well help you do the rest Youll be part of one of the worlds most exciting companies who are one of the leaders in semiconductor IP solutions, As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology, Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec ,

The candidate will be part of the R&D in Solutions Group in India The position offers learning and growth opportunities, This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design Verification using UVM based environment methodology, Job Description: The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release As part of the work, you will closely work with lead and be part of a global team of experienced Engineers, Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC, Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog, Hands-on experience with coverage closure and writing SVA for IP/SOC, Good simulation debugging skills, Experience with Perforce or similar revision control environment, Experience with Python/TCL or any scripting knowledge is an added advantage, Job Responsibilities Include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture Propose and enhance the UVM architecture with unique idea for verification, Be single point of contact with hands-on experience on all verification tasks Testbench Creation Testplan creation Coverage closure SVA Release Perform peer review of testbench code for continuous quality, Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure, Periodically publish technical papers and/or file patents on the feature updates/innovation carried out, The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide, In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative, This position requires prior industry experience and is not open for college fresh grads,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with a strong background in Static Timing Analysis (STA) and Synopsys Design Constraints (SDC) Your expertise in RTL and System Verilog, along with your proficiency in scripting languages like Perl, Tcl, or Python, makes you stand out You have a deep understanding of front-end EDA design methodologies and experience with logic synthesis tools Your prior experience with SDC tools and RTL simulation is a significant plus You are an excellent communicator, capable of producing detailed product requirement documents, and you have a knack for translating customer needs into actionable insights for our R&D team With a BS in Electrical or Computer Engineering and over 10 years of experience in STA/Synthesis/Front-End Flows, you are ready to take on a leadership role and drive innovation at Synopsys, What Youll Be Doing: Collaborating with customers to ensure our SDC Constraints solution meets their expectations, Developing and integrating design methodologies with other Synopsys products, Tracking customer engagements and communicating status with Marketing and Upper Management, Preparing and delivering technical presentations to customers and Field Application Engineers (FAEs), Creating customer training material related to our SDC Constraints solution, Routinely meeting with customers to understand their key priorities and communicating these internally, Providing technical direction to our R&D team and championing key customer requests, The Impact You Will Have: Enhancing customer satisfaction by ensuring our solutions meet their needs and expectations, Driving the integration of our SDC Constraints solution with other Synopsys products, enhancing overall product offerings, Improving communication and collaboration between customers, marketing, and upper management, Empowering customers and FAEs with comprehensive technical knowledge through effective presentations and training materials, Influencing product development by providing valuable insights and priorities from customer feedback, Ensuring the continuous improvement and innovation of our SDC Constraints solution, What Youll Need: Proficiency with STA, SDC, Proficiency with RTL, System Verilog, Strong understanding of front-end EDA design methodologies, Strong Perl, Tcl, or Python scripting skills, Prior experience with logic synthesis tools, Prior experience using or supporting SDC tools (a significant plus), Prior experience with RTL simulation and SVA (a plus), Sound communication skills, both verbal and written, Ability to produce detailed product requirement documents, BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows, Who You Are: You are a highly skilled and experienced engineer with a passion for technology and innovation You possess excellent problem-solving abilities and have a customer-centric mindset You are a great communicator and collaborator, capable of working effectively with cross-functional teams Your ability to translate complex technical concepts into actionable insights makes you a valuable asset to the team, The Team You will be a part Of: You will be part of the industry??s leading SDC Management product engineering team This team focuses on developing and enhancing our SDC Constraints solution, ensuring it meets the highest standards of quality and performance You will work alongside talented engineers and collaborate with various departments to drive innovation and customer satisfaction,

About the Role : We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products.This is what you are responsible for : - Synthesis and STA (static timing analysis).- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.- Professional experience with ECO implementation, both functional and timing closure.- Experience with multi-clock, multi-power domain designs and multi-mode timing constraints.- Familiarity with DFT insertion.- Familiarity with simulation, debugging tools, and working closely with Design teams.- Ability to collaborate with different functional teams like RTL Design, DFT and Physical design.- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Necessary Qualifications : - Bachelor's or Master's degree in Electronics, Computer Science Engineering, or a related field- Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA.- Experience with Cadence, Synopsys and Mentor tools- Experience with Verilog and VHDL.- Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP)- Formal verification for RTL 2 gates and gates2gates- Conformal ECO for doing complex functional ECOs.- Low power synthesis on smaller blocks and subsystems using DC/Genus- Physical Aware synthesis - Writing Timing Constraints sub-blocks and Top level.- Flow Automation and Scripting using TCL and Python or Perl.