500 System Verilog Jobs - Page 18

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test- cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans. ability to interface with different teams and prioritize work based on project needs.

We have a new demand for a GFXIP Emulation Methodology Lead for our client AMD, located in Bangalore . This is a high-priority requirement, and we are looking for candidates who can join immediately or within 15 days . Key Responsibilities: Exposure to Emulation model build and sanity bring-up Proven Emulation Testbench bring-up experience with C++ and SystemVerilog BFM models Expertise in porting C++/SystemVerilog Simulation Testbenches to Emulation Hands-on experience with SystemVerilog, C++ based testbenches BFM coding using C++ or SystemVerilog Strong Python scripting skills Exposure to GPU emulation model build and sanity bring-up Good understanding of GPU architecture Strong functional verification expertise Qualifications: B.Tech with 12+ years or M.Tech with 10+ years in Electronics and Communication Engineering (ECE) or VLSI

Responsibilities & Achievements: Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification) Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path, Negative tests Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. Successfully led a AV verification team of engineers across DV, emulation Key Skills Accelerated Verification: Synopsys ZeBu, Siemens Veloce Verification Methodologies: UVM, System Verilog, Acceleratable UVM, C based V&V Reuse & Bridging: Simulation-to-Emulation Flow, Coverage Continuity, Transactor Development is desirable.

Full-Time Role Overview We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

SE NIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, SOC design, design quality checks and design automation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design of Subsystems with integration of AMD and other 3rd party IPs Understand clocking, reset and soc top level topology changes to make connectivity as per the topology across IPs Collaborate with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated in SoC Understand SOC power domain requirements(power architecture) to write UPFs Perform quality checks: Lint, CDC, Low Power checks, Timing constraints, LEC for complex digital designs Identify areas for automation and create solutions to improve productivity and quality, continuously improve the automation process by exploring new tools and technologies PREFERRED EXPERIENCE: Proficient in Verilog and System Verilog with good understanding of RTL design flows and process Detailed understanding of SoC design flows Experience with version control system such as perforce Verilog lint(Spyglass) and simulation tools (VCS) Good understanding and hands-on experience in UPF, CDC, RDC, Timing constraints, LEC and other design quality check concepts Good with Scripting languages such as Python, Perl, Makefile, TCL and unix shell Automating workflows in a distributed compute environment Experience with embedded processors, data fabric architectures (NoC) and standard protocols such APB/AXI Stream and AXI MM Ability to work with multi-level functional teams across various geographies Strong problem-solving and analytical skills ACADEMIC CREDENTIALS: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major. #LI-SR5 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design Engineer The Person: If you have experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Lead a subsystem development team of 4 to 5 members. Preferred Experience: 5-7 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management(PM) techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the Design of new and existing features for AMD s IPs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the IP and/or new features to be designed Build design documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to design the new features and QA checks Documentation of the Micro Architecture Specification Work with the verification team to review the test plan and make sure all features are covered Debug test failures to determine the root cause; work with Verification and firmware engineers to resolve design defects PREFERRED EXPERIENCE: Proficient in IP level ASIC RTL Design Proficient in debugging firmware and RTL code using simulation tools Proficient in working with Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the SystemVerilog language and UVM based verification Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to DDR, SERDES or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Budget: 5x or 6x B.E./B.Tech or M.E./M.Tech in Electronics or a related field 12–16 years of experience in semiconductor/VLSI services with at least 3–5 years in delivery or practice leadership roles System Verilog,UVM,test case, coverage, regression Required Candidate profile Proven experience managing cross-functional teams and multiple client engagements. Exposure to EDA tools (Synopsys, Cadence, Mentor), scripting (TCL, Perl, Python

Role Proficiency: Provide leadership to a project with appropriate technical options and well suited design standards for embedded system product development system level validation and performance optimization strategies. Outcomes: Design develop and implement system level specifications. Develop highly optimized secured code debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP owners product (HW & SW) architects for design and debugging as per the project needs. Prepare Release Notes and participate in release strategies. Mentor lead and manage Developers I II III Embedded Software Engineers based on project needs Identify and recommend appropriate tools (SW & HW) for the project. Developing utilizing various debug validation tools and/or methodologies to implement Development and validation plans Create share best practices and lessons learned with the team. Optimises efficiency cost and quality. Influence and improve customer satisfaction Set FAST goals for self/team and also provide feedback to FAST goals of team members Measures of Outcomes: Adherence to embedded design process and standards Quick turnaround on multiple alternative solutions determining the most suitable Number of technical issues uncovered during the execution of the project Number of review feedback post Software Lead II review based on project SLA Number of design and test defects post-delivery based on project SLA Quick turnaround on defect fixing for design and tests based on project SLA Adherence to testing methodologies and compliance process Adherence to project schedule / timelines Deploy Innovation techniques and publish white paper Team management and productivity improvement as per Project SLA. Outputs Expected: Requirement: Lead requirement engineering; collaboration with internal and external customers to understand their needs Design: Embedded design architecture/LLD and linking to requirements Develop: Design the embedded SW and code as per design patterns coding standards templates and checklists. Develop automated tools or scripts for the validation environment. Test: Analysis and testing of prototypes validate the designed software document the analysis and test results Document: Create documentation for one's own work and contribute to creation of design HLD LLD/architecture for component/system software/ application diagnostics and test results Status Reporting: Report status of tasks assigned; comply with project related reporting standards/process Quality: Lead design reviews add value take responsibility for the design and overall quality of the embedded software Release: Adhere to release management process for circuit simulation design schematics board files Compliance: Adhere to embedded software design regulatory and test compliance Estimate: Estimate time effort resource dependence for one's own work and for projects' work. Accurately define and document the technical side of the project schedule with estimates and identified risks Interface with Customer: Clarify requirements and provide guidance to development team. Present design options to customers and conduct product demos Manage Project: Manage delivery of embedded software and manage requirement understanding and effort estimation. Manage Team: Set FAST goals and provide feedback. Understand aspirations of team members and provide guidance opportunities etc. Ensure team is engaged in project Manage Defects: Perform defect RCA and mitigation. Identify defect trends and take proactive measures to improve quality Manage knowledge: Consume project related documents and specifications. Review the reusable documents created by the team Skill Examples: Ability to create Embedded C Program Development for system level. Capability in creating and executing one or more of the following domains: Storage/connectivity/ Media/graphics/boot/clusters/ infotainment/ADAS Ability to do C++ programming (OOP) Assembly programming skills Ability to handle OS Scheduler Pre-emptive Round robin & Cooperative scheduling related work Ability to handle SW development in area of CAN Diagnostics Vehicle Functions etc. Aptitude in Networking protocols such as CAN LIN etc Ability to select right IoT & IO protocols as per problem statement. Ability to do Unit Testing (Tessy & RTRT) using appropriate Integration Testing Tools Ability to define and execute test cases with techniques (White Box and Black box) Ability in Closed loop LabCar INCA or similar tools Capacity to configure GDT framework. Ability to adhere to software quality standards (MISRA PCLINT QAC). Ability to debug using embedded tools Ability to do automation and configure Simulation Tools. Proactively ask for and offer help Ability to work under pressure determine dependencies risks facilitate planning and handle multiple tasks. Build confidence with customers by meeting deliverables in time with quality. Estimate effort time resources required for developing / debugging features / components Make decisions on appropriate of the Software / Hardwares. Strong analytical and problem-solving abilities Knowledge Examples: Knowledge on product development lifecycle Testing methodology and standards (Water Fall/ Agile) Knowledge in Test Automation scripting languages (e.g. Python Perl TCL) Knowledge with Wired (USB Ethernet PLC SCADA etherCAT Modbus RSxxx & Wireless technologies like NFC Bluetooth Wi-fi Zigbee etc. is a plus Understanding of automation frameworks (e.g. Hudson/Jenkin) Knowledge and knowhow on Diesel and Gasoline Engine Management Systems Knowledge of embedded algorithm integration on platform (Windows Linux and Android) Comprehension of ASPICE & ISO26262 process Knowledge in Pre-Silicon Verification environments for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem and SOC development environment Knowledge of MISRA 2004 and 2012 Coding guidelines (PC-lint LDRA & PRQA) Knowledge of CAN Tools: CANoe CANalyser & CAPL programming Knowledge of GDT framework internals Additional Comments: Role Proficiency: Provide leadership to multiple projects with appropriate technical options and well suited design standards for embedded system product development system level validation and performance optimization strategies. Account for others' developmental activities; assist project manager in day to day project execution Outcomes: Design develop and implement product level specifications for multiple projects. Develop highly optimized secured code debugging integrating firmware/ applications and development level testing of complex SW/HW systems. Work directly with IP owners product (HW & SW) architects for design and debugging. Mentor lead and manage the Lead I Embedded Software based on project needs Identify and recommend right tools (SW & HW) for the project. Developing and utilizing various debug and validation tools and/or methodologies to implement development and validation plans Create share best practices and lessons learned to the team. Optimises efficiency cost and quality. Influence and improve customer satisfaction Set FAST goals for self/team and also provide feedback to FAST goals of team members Select and create appropriate technical options for development such as reusing improving or reconfiguration of existing components or create own solutions for new contexts Influence and improve employee engagement within the project teams Prepare Software Quality Assurance Plan. Create Progress Reports and Process Review (Audit) Reports and Release Readiness ZBB (Zero Bug Build) Review report. Measures of Outcomes: Adherence to Embedded design and Quality process and standards Quick turnaround on multiple alternative solution and determine the most suitable one Number of technical issues uncovered during the execution of the project Number of design and test defects post-delivery based on project SLA Adherence to testing methodologies and compliance process Adherence to project schedule and timelines Number of new ideas implemented and patented as per business requirement. Percent of voluntary attrition On time completion of mandatory compliance trainings. Team management and productivity improvement as per Project SLA. Outputs Expected: Design: Embedded design architecture/LLD sequence/use case diagrams and linking to customer requirements Develop: Design the embedded SW and code as per design patterns coding standards templates and checklists. Test: Review and create unit test cases scenarios and execution Review test plan created by testing team Provide clarifications to the testing team Document: Create and review templates checklists guidelines standards for design/process/development Create and review deliverable documents. Design documentation requirements test cases/results Configure: Define and govern configuration management plan Ensure compliance from the team Domain relevance: Advise embedded software developers on design and development of feature / component with deeper understanding of the business problem being addressed for the client Learn more about the customer domain and identify opportunities to provide value addition to customers Complete relevant domain certifications Status Reporting: Report status of tasks assigned comply to project related reporting standards/process Quality: Lead design reviews add value take responsibility for the design and overall quality of the embedded software Release: Execute and monitor release process Compliance: Adhere to embedded software design regulatory and test compliance Estimate: Estimate time effort resource dependence for one's own work and for projects' work. Accurately define and document the technical side of the project schedule with estimates and identified risks Interface with Customer: Clarify requirements and provide guidance to development team present design options to customers conduct product demos Work closely with customer architects for finalizing design Manage Project: Manage delivery of embedded software and manage requirement understanding and effort estimation. Support project manager with inputs for the projects Manage Team: Set FAST goals and provide feedback understand aspirations of team members and provide guidance opportunities etc. Ensure team members are upskilled Ensure team is engaged in project Proactively identify attrition risks and work with BSE for retention measures Certifications: Take relevant domain/technology certification Skill Examples: Ability to do Embedded C, C++ programming (OOP) STL Assembly programming for product level. Ability to create and execute one or more of the following domains: Storage/connectivity/Media/graphics/boot/clusters/ infotainment/ADAS Ability to do Linux / Android kernel patching Back porting kernel patches and OOT merging; upstreaming to community Ability to develop solutions based Skills Embedded Software,Embedded C, Embedded C++, RTOS, IOT/Wireless/IOT.

About the Role We are seeking a highly skilled and experienced Hardware Architect to join our dynamic team. The ideal candidate will have a strong background in hardware architecture, particularly in writing architectural models and conducting performance and power analysis of chips. In addition to collaborating closely with our hardware team, the successful candidate will also work with our software department, which focuses on compilers, runtime software, and kernel software, to ensure cohesive and efficient chip design and functionality. This is what you are responsible for Architecture Modeling: Develop architecture models for AI chips. Collaborate with cross-functional teams to ensure models accurately reflect design specifications and requirements. Utilize industry-standard tools and methodologies for architecture modeling. Performance Analysis: Conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs. Use simulation and analytical methods to predict and enhance chip performance. Work with software teams to validate performance models with real-world applications and workloads. Power Analysis: Perform detailed power analysis to ensure AI chips meet stringent power consumption targets. Necessary Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field Minimum of 8 years of experience in hardware architecture/design of silicon chips Strong understanding of computer architecture principles and AI chip design. Proficiency in C/C++/Verilog. Define micro-architecture and write detailed design specifications. Implement complex digital functions and algorithms in RTL. Experience with synthesis, static timing analysis, and linting tools. Experience in any of processor subsystem design, interconnect design, high speed IO interface design.

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Sr Staff Engineer (VIP verification) Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 8839 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 7yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

Job Description: This is a full-time role for an FPGA Design Engineer at Agiliad Technologies in Pune. The FPGA Design Engineer will be responsible for tasks related to designing and developing products using Lattice and Altera FPGAs. Collaborating with cross-functional teams on product development. Job Title: FPGA Design Engineer Location: Pune Experience level: 4 -6 Years Responsibilities and Skills: In depth knowledge with VHDL/Verilog/System Verilog, Embedded C, RTL design, FPGA design, Knowledgeable about FPGA architecture. In-depth tool flow knowledge of FPGA design tools any of Xilinx, Altera, Lattice. Must be willing to learn new software tools. Complete FPGA development flow from logic design, place & route, timing analysis closure, simulation, verification, and validation Experience with Lattice/Altera FPGA families and corresponding development tools Experience of development & debugging firmware on FPGA based processors (Microblaze/Nios/Risc-V/Zynq-SoC). RTOS experience is added advantage. Experience in verification/simulation tools like Modelsim, code optimization to reduce resource usage, ability to understand synthesis reports, perform timing analysis and write FPGA design constraints, write testbenches for design verification Debugging and troubleshooting FPGA implementations on hardware boards Firsthand experience on communication protocols UART/SPI and bus interfaces AMBA/AXI. Knowledge of interfaces like, Flash, Ethernet, SerDES Memories like DDR. etc will be an added advantage. Understanding of Analog and digital Fundamentals, use of hardware such as oscillator and logic analyzers for hardware debugging. Qualifications: Bachelors/Master’s in Electrical Engineering, Computer Science, or related field. Proven experience in FPGA development, with a focus on low power consumption. Strong programming skills in hardware description languages (e.g., Verilog, VHDL) and experience with FPGA development tools. Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Excellent problem-solving and debugging skills. Strong interpersonal, communication, collaboration and presentation skills. Experience Level: Minimum 4 years of relevant experience in FPGA development.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74922 Description Responsibilities Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design and data converters. Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs. Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs. Ability to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions. Competent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs. Experienced in producing detailed technical reports and documentation. Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred. Experienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc. Simulation performance and accuracy trade-offs based on design requirements Experienced in Power-aware mixed-signal verification Hands-on verification of sub-45nm CMOS SOC designs Desired Experience and Skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Job Segment: Electrical Engineering, Design Engineer, Telecom, Telecommunications, Network, Engineering, Technology

Hiring Freshers Kickstart Your Career in VLSI At PRSsemicon Technologies, we are shaping the future of semiconductor innovation by building a Global Capability Development Centre. We are looking for fresh graduates passionate about VLSI domains to join our team. Through structured training and hands-on experience, we ensure you gain the technical expertise and industry-relevant skills required to succeed in this dynamic field. Your Journey with Us: Comprehensive Training Gain in-depth knowledge of VLSI design, verification, emulation, DFT, physical design, and analog design based on project needs. Hands-on Experience Work with industry-standard tools and methodologies. Expert Guidance Learn from seasoned professionals and build practical expertise. Live Project Transition Successfully complete training and contribute to real-world chip design projects. What We Look For: Strong fundamentals in Digital Electronics. Eagerness to learn and build competency before taking on project responsibilities. Passion for VLSI design and a commitment to a long-term career in semiconductors. Why Join PRSsemicon? Be part of Indias thriving semiconductor industry. Learn from experienced professionals in a structured training environment. Get hands-on exposure to cutting-edge chip design projects. Headquarter: Chennai Mode: Offline/Online/Hybrid (as per project requirements) Eligibility: B. Tech/M. Tech in ECE, EEE, E & I, VLSI, or related fields Year of passing out: From 2022 and below (2021, 2020.. ) will be considered Apply Now & Shape the Future of VLSI with Us!

Exp: 12 to 16 years B.E./B.Tech or M.E./M.Tech in Electronics semiconductor/VLSI services with at least 3–5 years in delivery or practice leadership roles. Experience in System Verilog, UVM, test case, coverage, regression.

Skills: Programming Language : Strong in VHDL along with Working knowledge on Verilog/System-Verilog Preferable Skills: * Use of tools such as Quartus, Vivado, Libero and their IPs * Experience with using any simulator (Modelsim, XSIM, etc.) * Deep understanding of FPGA design flow including RTL design, verification, logic synthesis, timing analysis, floor-planning, ECO, bring-up & lab debug. * Experience with gate-level understanding of RTL and synthesis * Experience with basic lab equipment such as Logic analyzers, scopes, protocol analyzers, etc. * Development experience and board level debugging on Ethernet (1G, 10G) experience is preferable * Experience in DDR3/DDR4 is preferable * Experience in AMBA/AXI is preferable * Good interpersonal and communication skills Vhdl

Job Category: Engineer Job Type: Full Time Job Location: Bangalore Join Mettlesemi s DFT design team to develop next-gen chips with a revolutionary architecture. Contribute to a multifaceted DFT approach, including architecture definition, logic design, verification, test pattern generation, and chip bring-up. Work in a dynamic, open, and fast-paced environment on cutting-edge silicon chip technologies. Shape the future of chips for top-notch clients. KEY JOB RESPONSIBILITIES: Senior DFT Engineer pivotal in device lifecycle, from definition to mass production. Collaborate with VLSI groups (chip design, verification, backend, test, and reliability). Develop, implement, and verify DFT on complex SOCS. Work closely with architecture team for DFT understanding. Ensure DFT design rules compliance with design teams. Collaborate with physical design team to meet DFT requirements. Expertise in SOC-level DFT techniques (ATPG, MBIST, JTAG, boundary scan). BASIC QUALIFICATIONS 6+ years chip design experience. 4+ years as a DFT engineer in a semiconductor company. Bachelor s/Master s in Electrical/Electronics Engineering. Strong post-silicon DFT bring-up and debug experience. Hands-on experience with multi-vendor DFT tools. Proficiency in ATPG tools (Mentor TK). Exposure to static timing analysis; timing closure. Excellent scripting skills in Perl/Tcl/Tk/Python. Knowledge of DFT technologies (JTAG, MBIST, Scan). Experience with RTL Coding (Verilog, System Verilog, VHDL). PREFERRED QUALIFICATIONS: Expertise in DFT methodologies (scan insertion, scan compression, boundary scan, memory BIST). Experience with DFT tools (Tessent, ATPG, MBIST, JTAG). Proficiency in Shell/Perl/Tcl and other scripting languages. Familiarity with ATE. Chip design, Verilog, and System Verilog. Verification, UVM methodology. ATPG tools, scan insertion tools, gate-level simulations. Static timing analysis. Scripting (Perl/Tcl). INTERPERSONAL SKILLS: Energetic, self-motivated Leader and Team player Proactive, detail-oriented, and quality-focused. Strong communication and reporting skills. Ability to collaborate with cross-national partners

Job Category: Design Verification Job Type: Full Time Job Location: Bangalore Requirements: Bachelor s / Master s degree in Electrical Engineering or Computer Science with 6+ years of relevant experience Verilog / System Verilog based verification experience at Subsystem and Full chip level. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with System Verilog Assertions with industry standard tools a plus Experience with SOC bot flow, clocking and platform bring up in Emlators or Silicon Desired Experience with Low Power Verification and power management flows. Experience with RTL, GLS level simulations Knowledge and experience working on PCIE/Ethernet and other HSIO desired Experience in UVM/OVM based methodology Development. Responsibilities: Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/Sytem Verilog Create complex C/SV tests using reusable test libs Team player and mentor who is self-driven, motivated and guides a team of junior engineers Responsible for quality and timeliness of the team output

Job Category: Design Job Type: Full Time Job Location: Bangalore About Us: Mettlesemi Systems and Technologies Pvt Ltd, based in Bengaluru, specializes in providing embedded systems, silicon solutions and related services. We have strong partnerships with top oplayers in the Semiconductor and Embedded Systems domain, across product development and prototyping. The Role: Mettlesemi is looking for exceptional engineers and engineering leaders to join our SOC development team to develop cutting-edge products within disruptive system architecture. You will have the oppertunity to work on the latest technologies in silicon chip design within a dynamic, open, and fast-peaced environment and develop the next generation of chips based on revolutionary architecture for our top-notch clients. Key Responsiblities: We are looking for talented Senior engineers to join our top-tier teams and participate in design and verification activities working on next-generation products, starting from the identification and definition of project requirements, architecture, and feature development. As a Design Engineer and integral part of the project team, your responsibilities will encompass the development of intricate Microarchitecture, Logic Design, Synthesis, Timing Closure, and Formal Verification using Formality. Collaboration with the Design Verification Team, the DFT Team, the Physical Design Team and other stakeholder teams will be a key aspect of your role. This presents a unique opportunity for you to make a significant impact across the entire product lifecycle. In this role, you will work in a team developing SoCs to be deployed in a range of products/applications. You will integrate industry-standard and custom hardware IP and subsystems into SoCs and will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals for these products/applications. BASIC QUALIFICATIONS 6+ years of experience in chip design. 5+ years or more of practical semiconductor design experience. Proficiency in Verilog/System Verilog. Fluent in scripting languages (TCL, Python). BE degree in Computer Engineering/BS Computer Science/Electrical Engineering. Excellent verbal and written communication skills. Strong collaboration and teamwork skills, ability to contribute to diverse and inclusive teams. PREFERRED SKILLS/EXPERIENCE Experience with the full SOC cycle Synthesis/STA/CDC/Lint. Experience with successful tape-outs of complex, high- volume SoCs in advanced design nodes. Experience with Design Automation. Experience in Designing protocols such as AMBA, LPDDR, DDR4 Strong working knowledge of Network on Chip (NOC), Coherent, and non-Coherent fabrics.