1277 System Verilog Jobs - Page 21

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Circuit design. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Embedded and System Software. Experience3-5 Years.

We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure Zero Defect chips Collaborate with SME s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI. Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 14 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell . Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

CPU Verification Engineer in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: As a CPU Verification Engineer, you will be a key member of the design verification team at Ampere to deliver our high-quality next generation AI integrated, cloud-native server class SoCs. You will be responsible for defining verification strategies and architecting solutions for complex verification problems. You will partner with stakeholders in adjacent domains and enable verification team to left shift bug hunting and meet verification goals on schedule. Youll be involved with all aspects of product development starting with specifications through tape-out and product launch Define strategy and requirements for block level and chip level testing infrastructure Create test plans for unit-level and chip-level verification Design and implement test benches and verification environment Develop random test generators to generate tests and debug failures Code and analyze coverage to meet product quality requirements Define post-si validation plans and debug post-silicon system level failures B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience, or M.Tech with 2+ years of experience. Understanding of high-performance multi-core processor architecture and microarchitecture Knowledge of ARM or x86 memory architecture and assembly language is advantageous 2+ years of IP design verification experience, especially in CPU or Graphics cores, with previous experience in IP verification, particularly microprocessor core or interconnect/fabric Experience with verification environments using SVTB, UVM, or OVM Proficiency in HDL languages (System Verilog, Verilog, VHDL) and simulation tools Programming skills in C or C++ Ability to automate tasks using Perl, Python, or other scripting languages Experience with Uncore CPU features like Trace / Debug / Interrupts / Performance Monitoring is a plus Strong communication, problem-solving skills, and a verification-focused mindset. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The role will focus on RTL design and full chip integration and projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc. The role requires to work with architect and micro-architect team to understand define design specifications The successful candidate will be open and willing to both (a) teach best-known-methods to an existing design team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. Accountabilities: Serve as a key contributor to RTL design efforts. Drive logic design of key blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality through assertions, checkers, and scripting. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 5+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus. Familiarity with FPGA designs, use-cases, and design considerations is a plus. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Lattice Semiconductor is seeking a Design Engineer-2 FPGA Architecture to join the Architecture team focused on FPGA architecture modeling and advance system architecture. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in architecture modeling and evaluation of Lattice FPGA s and Software tools to measure performance, power, and area for various workloads The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with Software tools team to define benchmarks, measure performance and suggest improvement areas Serve as a technical expert, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and open-minded student Accountabilities: Serve as a key contributor to build FPGA architecture modeling and evaluation platform efforts Drive logic design of key FPGA workloads and bring best-in-class methodologies to accelerate design and test time and quality. Develop the regression testing framework to execute, measure and report architecture modeling and evaluation experiments Ensuring design quality throughout project development conducting regular reviews and audits Perform architecture evaluation of competitive products Work with cross functional team including program management, Software Tools, HW architects, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up to date with the latest industry trends and technologies Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 3+ years of experience in driving logic design across a multitude of FPGA projects. Expertise in FPGA designs, use-cases, and design considerations, defining micro-architecture and experience of working with various EDA tools Experience in leading the project throughout design cycle and working with cross organization Proven ability to work with multiple groups across different sites and time zones. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry s technology leadership. An opening exists for Technical Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you wont just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment youd like to participate in, wed like to hear from you! As a Technical Staff Design Engineer, your job will entail the following: Lead the Design planning of pad rings and package substrates, bump pattern construction. Dynamically define and optimize pad ring connectivity. Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,) Interface with and support Architect, PD, PE, technology development and foundries teams. Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds. Additional responsibilities include: Collaborate closely with the Manager to define team structure, skill requirements, and hiring strategy for the local IP development team. Support and participate in end-to-end recruitment activities, including job description creation, candidate screening, interviews, and onboarding. Help identify and engage top technical talent through various sourcing methods in alignment with project and business goals. Assist in establishing a strong, high-performance team culture by supporting team integration, training, and knowledge-sharing initiatives. Work cross-functionally with HR, Talent Acquisition, and Engineering leadership to ensure a streamlined hiring process and effective team ramp-up. Contribute to the development of a scalable team that aligns with long-term IP roadmap and organizational growth. Requirements/Qualifications: B.S or M.S degree in electrical engineering with 12+ years of related experience Prior experience in IC and multicore SoC designs Experience with front-end CAD tools (eg. top-level I/O planning tools) is required. Experience with Verilog/System Verilog is required Familiarity with Verilog models and Liberty files Experience in Fin-Fet technologies is a plus. Scripting experience or knowledge is a plus. Excellent analytical, communication (written and verbal), and documentation skills Excellent problem solving and debugging skills. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

MIPS is seeking a skilled and motivated Design Verification Automation Engineer to develop advanced flows for CPU development. The candidate will build on existing modern methodologies to improve and support current infrastructure and create new solutions. They will work closely with lead developers in support of quality, efficiency, and predictability of execution through scripts, flows, and internal and third-party tools. The ideal candidate will have experience with CPU design verification development methodology and a solid background in software and flows. Required Skills: Python scripts and automation C, C++ Jenkins management Jira integration Familiarity with git or perforce LSF or Grid management Supporting Experience: Design Verification methodology Cadence or Synopsys verification solutions System Verilog, UVM CPU architecture, development, and software Database development Here s what you can expect from us: At MIPS, you ll be a member of a fast-growing team of technologists that are creating the industry s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure - you ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry s most experienced CPU engineers. An unlimited growth path - with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers. At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! More about us: MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

System Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of IPs for the next generation of compute solution. .You will work closely with architecture, design, verification, modelling, performance analysis, SW development, Emulation and FPGA and Board development engineers. Responsibilities: Work with project team to understand, review the system requirements and deliver emulator testbench specifications. Key responsibilities will include owning the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc) in emulation environment. Will guide other members of the team as needed to enable the successful completion of project activities Required Skills and Experience : Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering - although other degrees will be considered with relevant work experience You will need experience of Emulation and system level validation for IPs and sub-systems and ASIC products. Emulation build skills and knowledge for a subsystem in at least one emulation system is required. Execution of the design in emulation platform and knowledge of hardware and software interplay is required. You possess the knowledge of Validation test content using C, C++ etc and how they can be performed in an emulation-based system. Expertise on hardware behavioral language (Verilog, System Verilog) Exposure to producing validation specifications and documentation describing sophisticated designs Ability to work under time-scale pressure and meet ambitious targets without compromising on quality Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator. Practical experience of working on Processor based system designs Nice To Have Skills and Experience : Demonstrated understanding of CPU/ GPU subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan. Hands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems. Understanding of SoC security aspects

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are looking for Senior SOC Verification Engineers for the Hyderabad location. 1) SOC Verification 2) SV UVM 3) DDR, PCIe, Ethernet. Interested candidates, Kindly Share with me your updated profile with Naveen.a@modernchipsolutions.com

Strong in digital design. Skills in ASIC/FPGA verification(directed test or SV/UVM) A good knowledge of simulation flow. Good scripting knowledge Perl/python Share your Resume to mansoor@hisoltech.com

Experience with OVM/UVM/VMM/Test Harness, developing assertions, checkers, coverage, and scenario creation.,min 2 to 3 SoC Verification projects.developing test and coverage plans, verification environments, and validation plans,

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuitblocks, including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks, aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing, and other critical activities extending beyond the design phase. Your Profile You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone.

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

Job Description Must have: Must Have Required Expertise: Should be able to build test plan, tests, coverage assertions from Specification. Architect and build testbench and testbench components. Good in UVM,SV,C SVA. Familiar with industry protocols, such as AXI, APB, AHB, PCIe, SoC. Very good in debugging. Worked with industry standard EDA tools Synopsys, Cadance simulators and debugging tools. Good to have skills: Experience with scripting and automation. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS and a proactive approach to automation. Exposure to SOC verification, Formal verification methodologies.

MTS SILICON DESIGN ENGINEER THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics PREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in block level NOC (Net work on Chip) verification is a plus. Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74922 Description Responsibilities Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOCs at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. Required Experience and Skills 8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience Expertise in developing testbenches using System Verilog and UVM Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations Strong object-oriented programming knowledge using SystemVerilog Strong problem-solving and debug skills capable of isolating problems to the block level Expertise in developing test plans, implementing coverage models, and analyzing results Experience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc) Familiarity with C-code/embedded firmware/debuggers Ability to work in a dynamic environment with changing needs and requirements Ideally you are also experienced in: Using Formal verification methods and tools like Jasper Gold. Real-time data processing systems Audio signal processing Audio performance concepts (SNR, THD, SINAD, DR, etc.) Familiarity with standard interfaces (SPI, I2S, PDM, PWM, USB, etc.) Familiarity with wireless protocols (Wi-Fi, BLE, BT, MAC/PHY) Familiarity with wireless different processors (ARM, HiFi, RISC-V) FPGA hardware emulation Desired Experience and Skills Job Segment: Electrical Engineering, Network, Telecom, Telecommunications, Firmware, Engineering, Technology