SoC RTL Design - Memory Team

As an experienced candidate with 6 to 15 years of experience, you will be responsible for the following: - Architecture, Micro-Architecture, Design, and RTL development for storage controller IP's based on UFS, NVMe, SAS, NVMeOF, eMMC, and high-speed peripheral bus standards such as PCIe. - Interfacing with cross-functional teams like Verification, Validation, and FW to ensure seamless collaboration. - Ensuring the quality of design by conducting Lint and CDC checks. - Synthesis, Area, and power optimization to enhance the performance of the storage controllers. - Developing timing constraints (SDC) and ECO scripts to streamline the design process and ensure quality deliverables and reuse. Your role will also involve: - Leading the team technically and providing guidance. - Utilizing Verilog/System Verilog/VHDL for Architecture, Micro-Architecture, Designing, and RTL coding. - Working on complex IP Design in high-speed serial protocols like UFS, PCIe, SAS, NVMe, and Fabrics. - Conducting Design QC using lint/CDC/DFT and performing compile, elaboration, and simulations for QC. - Experience with VCS, NCSIM, Verdi, and Spyglass tools. - Synthesis using Synopsys Design Compiler (DC) and developing timing constraints (SDC) for Timing analysis. - Understanding storage controller Architectures, Peripherals, Buses/Interconnects, and Power Management. - Knowledge of Bus Architectures (AXI/AHB), NOC (Network-on-Chip), and ARM CPU Architectures. About the Company: Samsung Semiconductors India R&D (SSIR) is one of the largest overseas R&D centers of the Semiconductors Business of Samsung Electronics. The team of engineers at SSIR works on advanced semiconductor technologies, contributing to reliable, high-performance solutions that are part of many well-received Samsung products. The Memory Solutions Team (MST) Controller development focuses on designing cutting-edge storage controllers for SSD based on NVMe, UFS, SAS, NVMe over Fabrics, and high-speed peripheral bus standards like PCIe.,