Physical Design - SOC / GPU Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer, you will be responsible for the complex SOC top physical implementation of next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of both complex blocks and full-chip designs. You will be expected to demonstrate expertise in top-level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. A strong understanding of timing, power, and area trade-offs, as well as optimization of PPA, will be crucial for success in this role. The ideal candidate will be a power user of industry-standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality, and should be able to leverage their capabilities effectively. Proficiency in scripting languages like Perl and Tcl, along with a deep understanding of implementation flows, will be essential. Experience with large SOC designs exceeding 20M gates and operating at frequencies above 1GHz is highly desirable. You should possess expertise in block-level and full-chip SDC clean up, Synthesis optimization, Low Power checking, and logic equivalence checking. Familiarity with deep sub-micron designs, particularly at 8nm and 5nm nodes, and associated challenges related to manufacturability, power, signal integrity, and scaling, will be advantageous. Understanding typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions is also important. You should be well-versed in hierarchical design, top-down design, budgeting, timing, and physical convergence. A good understanding of Physical Design Verification methodology to debug LVS/DRC issues at both chip and block levels is expected. Ideal candidates will have participated in recent successful SOC tape-outs, showcasing their ability to deliver high-quality designs.,

Posted 2 days ago

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Engineer, ASIC Design kinara

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

Posted 3 days ago

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