8 Area Optimization Jobs

As a VLSI Engineer with 5-6 years of experience in the semiconductor industry, your role will involve working on complex SoC designs, collaborating with cross-functional teams, and delivering high-quality silicon solutions. Your key responsibilities will include: - Designing and developing RTL using Verilog / SystemVerilog for ASIC/FPGA. - Performing functional verification using UVM / SystemVerilog based testbench. - Working on synthesis, timing analysis, power analysis, and design for testability (DFT). - Collaborating with physical design, firmware, and validation teams to ensure design quality. - Understanding semiconductor process technologies and device physics. - Participating in desi...

As an experienced candidate with 6 to 15 years of experience, you will be responsible for the following: - Architecture, Micro-Architecture, Design, and RTL development for storage controller IP's based on UFS, NVMe, SAS, NVMeOF, eMMC, and high-speed peripheral bus standards such as PCIe. - Interfacing with cross-functional teams like Verification, Validation, and FW to ensure seamless collaboration. - Ensuring the quality of design by conducting Lint and CDC checks. - Synthesis, Area, and power optimization to enhance the performance of the storage controllers. - Developing timing constraints (SDC) and ECO scripts to streamline the design process and ensure quality deliverables and reuse. Y...

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Role Overview: You will be responsible for developing custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers. Your tasks will include performing detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf cell layout, and compiler assembly coding. Additionally, you will conduct complete layout verification, ensuring design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. You will use custom autorouters and custom placers to efficiently construct layout. Your role will also involve providing feedback...

As a member of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. **Key Responsibilities:** - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Carry out Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in ...

As an experienced professional in the field of semiconductor design, you will be involved in working on advanced technology nodes such as 7nm/5nm or lower, collaborating closely with a diverse range of customers to deliver cutting-edge solutions. Your role will primarily revolve around addressing and resolving critical design issues to meet performance, area, and power requirements. One of your key responsibilities will be to develop innovative flows and methodologies for efficient placement, clock tree synthesis (CTS), and routing. Your expertise in these areas will be instrumental in ensuring the successful implementation of complex designs and meeting project goals effectively. Additional...

As a Physical Design Engineer, you will be responsible for the complex SOC top physical implementation of next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of both complex blocks and full-chip designs. You will be expected to demonstrate expertise in top-level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. A strong understanding of timing, power, and area ...

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL ...