42 Ncsim Jobs

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We&aposre Looking For Bachelors degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Masters degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion/MBIST/ATPG/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met.Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required.Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NCSim, or Xcelium in GUI mode. Working with fault models including Stuck-at Faults and Transition Delay Faults (TDF) will be part of your role. You will also be responsible for optimizing and improving scan test coverage using established DFT techniques. The required skills and experience for this position include 5+ years of relevant experience in DFT, hands-on expertise with tools from Cadence, Siemens Tessent, and Synopsys, proficiency in debugging and analysis using VCS, NCSim, or Xcelium, strong analytical and problem-solving skills, and good communication and collaboration skills. Preferred qualifications for this role include experience in DFT automation using scripting languages like TCL, Perl, or Python, and prior exposure to automotive, networking, or high-performance computing SoCs is considered a plus.,

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Cadence tools,scan insertion,JTAG,ATPG,DRC,coverage analysis,simulation debug,timing,SDF,LBIST,Mixed Signal Radar IC,proactive,collaborative,detail-oriented,independent judgment,debug,root cause analysis,Verilog*

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DFT

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-date with industry trends and emerging technologies in DFT engineering. Job Requirements Strong understanding of digital logic design principles and microelectronic circuits. Experience with programming languages such as C++, Python, or Java. Familiarity with testing frameworks like JUnit, PyUnit, or Selenium. Knowledge of version control systems like Git. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate technical ideas clearly.

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Are you interested in a unique opportunity to be a part of something great Would you like to join a 20,000-member team that is at the forefront of technology that powers the world around us Microchip Technology, Inc. offers an environment of trust, empowerment, respect, diversity, and communication. You will have the chance to own a piece of a multi-billion dollar global organization and more. At Microchip, employees are part of a culture that supports growth and stability. They are engaged and motivated by a wide range of products and solutions with unlimited career potential. The nationally-recognized Leadership Passage Programs at Microchip facilitate career growth for over a thousand individuals annually. The company is committed to employee development, values-based decision making, and fostering a strong sense of community based on its Vision, Mission, and 11 Guiding Values. This commitment has earned Microchip numerous awards for diversity and workplace excellence. As a Verification Engineer at Microchip, your responsibilities will include playing a key role in block-level verification. You will develop verification test plans based on design specifications, create test environments using System Verilog and UVM methodologies, and integrate with RTL while conducting basic simulation bring-up for the design. You will be tasked with generating code/functional coverage, analyzing coverage results, correlating them with the test plan, creating multiple test cases, and launching regressions. Additionally, you will collaborate with the design team to quickly identify and resolve design issues. The ideal candidate for this role will have expertise in domains such as AHB, AXI, PCIe, USB, and Ethernet. Proficiency in Verilog and System Verilog is essential, as well as familiarity with at least one of the following methodologies: OVM, UVM, VMM. Experience with EDA tools like Questasim, VCS, NCSim, or NCVerilog is required. You should have experience in developing test bench components at both block and SOC levels, creating test plans, and writing test sequences. Knowledge of functional coverage, code coverage, and assertions (OVA, SVA, PSL) is desirable. Strong analytical, problem-solving skills, excellent written and verbal communication in English, and a passion for teamwork and excelling in a competitive environment are also essential. Qualifications for this role include a Bachelor's Level Degree (ECE, EE / preferred specialization) with more than 9 years of work experience. The role may involve up to 25% travel time. Please note that Microchip Technology Inc. does not accept unsolicited agency resumes. Kindly refrain from forwarding resumes to the recruiting team or other Microchip employees, as the company is not responsible for any fees related to unsolicited resumes. Visit our careers page to explore exciting opportunities and company perks.,

As an experienced VLSI SoC RTL designer with 10 to 15 years of work experience, you will play a crucial role in securing an optimal digital IP and circuit. Your responsibilities will include designing and verifying functions in alignment with the required goals. You will have the opportunity to contribute to various areas such as SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, and Flash Subsystem based on your skills and interests. To excel in this role, you should have a strong understanding of digital design principles, with specific knowledge of AMBA SoC BUS protocols like APB, AXI, and AHB. Your tasks will involve creating micro-architecture and detailed design documents for SoC design while considering performance, power, and area requirements. Proficiency in debugging and experience with DV tools such as Verdi and NCSIM will be essential. Preferred candidates will have SOC integration experience at the Top Level, Block Level, or Subsystem level. Collaboration with the DV team to enhance verification coverage and working on GLS closure with DV, PD, and Modelling team will be part of your responsibilities. Knowledge of clock domain crossing (CDC), Linting, UPF, ASIC Synthesis, static timing reports analysis, and formal checking is required. Furthermore, you will be involved in defining constraints and ensuring critical high-speed path timing closure in collaboration with back-end teams. If you are seeking a challenging opportunity to leverage your VLSI SoC RTL design skills and contribute to cutting-edge projects, this role offers a stimulating environment to grow and excel.,

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification. Good Understandingof GLS simulations Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis. Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs. Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns. Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Candidates need to have good experience in Tessant tools Candidates need to have good experience in ATPG pattern generation and simulation(both timing and no timing) Candidates need to have good experience in Scan insertion Experience should be more than 6+ years Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas

Number of Open Positions: 7 Experience: 4 to 7+ years Location: Bangalore : We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. Key Responsibilities: DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities. Verification: Verify DFT features and ensure their correctness through simulation and formal verification. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field. 4 to 7+ years of experience in DFT-DV engineering. Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG. Proficiency in industry-standard EDA tools for DFT implementation. Experience with low-power design and PHY-LP integration is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. SOC level Mixed Signal and High Speed Interfaces verification Engineer Experience of 1 year to 6 years in Design Verification Responsible for RTL and GLS level validation at SOC. Post Silicon validation support Familiarity with basic concepts of SV, UVM and C-based test case bringup. Understanding of GLS simulations and debug is a plus. Good in communication. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl).

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Description: Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification- Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education