11 Timing Constraints Jobs

Qualcomm India Private Limited is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. The WLAN PHY team in Bangalore specializes in taking WLAN PHY designs from concept to silicon independently. As a member of the team, you will be responsible for developing end-to-end Tx/Rx DSP chains, working on signal processing functions, and contributing to the development and enhancement of signal processing algorithms. Passion for the work and pride in your contributions are essential qualities we are looking for. The ideal candidate will have 1 to 3 years of experience in micro-architecting and developing complex IPs, expertise in digital design, and proficiency in RTL coding. Familiarity with RTL QA flows and proposing design alternatives to meet specifications are expected skills. Experience in leading, guiding, or managing junior team members, as well as success in taking IP designs from requirements to silicon, are advantageous. While not mandatory, experience with wireless technologies or HLS would be beneficial. Required skills include proficiency in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl, and experience in designing and debugging complex data-path/control-path IPs. Good communication, analytical, and leadership skills are essential. A Bachelor's, Master's, or PhD degree in Computer Science, Electrical/Electronics Engineering, or a related field is required, along with relevant work experience. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you would like more information about this role, please contact Qualcomm Careers.,

As a Senior Silicon Design Engineer at AMD, you will play a key role in contributing to the development and verification of cutting-edge technologies that drive innovation in the computing industry. Your passion for modern processor architecture, digital design, and verification will be instrumental in ensuring the highest quality products are delivered to the market. In this role, you will collaborate with a diverse team of engineers to implement front-end designs from RTL to netlist, conduct formal verification checks, and debug any timing, area, or congestion issues that may arise. Your ability to analyze inter-block timing and develop timing constraints will be crucial in optimizing the performance of the designs. Key responsibilities include running logic/physical synthesis, performing power estimation, and developing automation scripts for various front-end tools. Your strong analytical and problem-solving skills will be essential in identifying and addressing potential design issues, as well as working closely with architects, RTL designers, and SOC teams to ensure efficient IP quality. To excel in this role, you should have 5 to 10 years of experience in front-end implementation, familiarity with power analysis, and a background in computing/graphics. A Bachelor's or Master's degree in computer engineering or electrical engineering is required to be successful in this position. Join us at AMD and be part of a team that is dedicated to pushing the limits of innovation and solving the world's most important challenges. Together, we advance towards a future where technology enriches lives and transforms industries.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

As a highly motivated and innovative digital design engineer at Synopsys, you will play a crucial role in driving the innovations that shape the future in the Era of Pervasive Intelligence. Your expertise in ASIC design methodology and flows, particularly focusing on low power analysis and optimization, will be instrumental in empowering the creation of high-performance silicon chips and software content. With a proven track record in working with advanced nodes, especially at 5nm and below, you will be responsible for developing and driving digital design methodologies to achieve the lowest power consumption. Your strong background in both digital and physical design, coupled with your proficiency in developing timing constraints and UPF, will enable you to meet stringent power, timing, and area targets effectively. Collaborating closely with design teams and EDA tools teams, you will contribute to enhancing the power efficiency of high-performance silicon chips and driving innovation in low power design methodologies. Your role will involve conducting SAIF-based analysis, implementing best practices for low power design, and optimizing RTL designs to achieve optimal power consumption. To excel in this role, you will need to possess an MSEE or BSEE with over 20 years of digital design experience, including 15+ years of digital and/or physical design experience. Your expertise in low-power design techniques at RTL, proficiency in EDA tool flows, and excellent software and scripting skills (Perl, Tcl, Python) will be key to your success in this position. As part of the Digital Methodology Center of Excellence within Synopsys" IP team, you will collaborate with experienced engineers to develop cutting-edge digital design methodologies used across all IP development teams. Your organizational and communication skills, coupled with your ability to think and communicate at different levels of abstraction, will be essential in contributing to the successful implementation of advanced node technologies and industry-leading mixed-signal products. In addition to the challenging and rewarding work environment, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what is possible. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. These systems encompass a wide range of components such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your work will contribute to the development of cutting-edge, world-class products that drive digital transformation and enable next-generation experiences. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the relevant field will also be considered. As a Hardware Engineer at Qualcomm, your responsibilities will include front-end implementation of SERDES high-speed Interface PHY designs, RTL development and validation, collaboration with the functional verification team, development of timing constraints, UPF writing, DFT insertion, ATPG analysis, and support for SoC integration and chip level pre/post-silicon debug. The ideal candidate for this role should possess an MTech/BTech in EE/CS with 4 to 7 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA, high-speed interface design, and industry-standard protocols like USB/PCIe/MIPI. Experience with post-silicon bring-up and debug is considered a plus, along with the ability to collaborate effectively with global teams and excellent communication skills. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not entertain any fees related to such submissions. For further information about this role, you can contact Qualcomm Careers for assistance.,

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as familiarity with parasitic extraction tools and flow. Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog is required, along with a strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. In this role, your responsibilities will include driving sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs across various methodologies and technologies, as well as work on prototyping subsystems to deliver optimized PPA recipes. Collaboration with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology is essential. Furthermore, you will engage with foundry partners to enhance signoff methodology for improved convergence and yield.,

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

What You ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC RTL Design. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive leader with excellent managerial skills. A team player who can mentor and guide engineers. An effective communicator who can interact with customers and stakeholders. A problem-solver with a keen eye for detail. An innovator who continuously seeks to improve processes.

Senior Staff / Staff Physical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE + 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Principal / Principal / StaffPhysical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE + 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"