OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE As part of Safety and Automotive Center of Expertise, the key responsibilities shall be in definition of reusable SoC/IP safety design solutions for Industrial and Automotive products, with the goal to compute & minimize the system to silicon costs while assuring the adequate functional safety integrity level, verified through safety analysis (FMEDA, DFA, FTA). You shall also be responsible for defining and tracking the project safety plans & activities for the automotive products compliance to ISO26262, creating direct link with all product development functions. Your Skills & Experiences MTech/MS in VLSI or similar Up to 2 years experience in HW design & architecture and functional safety activities Working Knowledge and Skills on ISO 26262 & IEC 60958 standards is strongly required Elementary knowledge of Functional safety architecture and solutions for automotive & industrial micro-controllers, infotainment & ADAS products Awareness of Digital/Analog design development process ranging from specification development through RTL development until implementation closure Strong verbal & written communication skills Working experience on excel and VB based scripting Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers Show more Show less
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE 1) Audits Business managers submissions of Budgets and validates Results 2) Checks HR Feeds for changes in Plans, Employee details & updates records. 3) Publishes data requested by the Sales teams, HR, Business managers, Finance. 4) Finalises monthly accrual, forecasts, payments of the Sales incentives. 5) Performs and secures approvals for the split searches, adjustments, Rep commission. YOUR QUALIFICATION & EXPERIENCE 1) Graduation degree with specialisation in Finance : BBA / MBA 2) 3-5 years or prior experience in managing sales incentives. SKILLS 1) Expert working knowledge of Excel and Power BI 2) Excellent command over written and spoken English. 3) Skills to perform and flourish in a GBS environment. 4) Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE Audits Business managers submissions of Budgets and validates Results Checks HR Feeds for changes in Plans, Employee details & updates records. Publishes data requested by the Sales teams, HR, Business managers, Finance. Finalises monthly accrual, forecasts, payments of the Sales incentives. Performs and secures approvals for the split searches, adjustments, Rep commission. Your Qualification & Experience Graduation degree with specialisation in Finance : BBA / MBA 3-5 years or prior experience in managing sales incentives. Skills Expert working knowledge of Excel and Power BI Excellent command over written and spoken English. Skills to perform and flourish in a GBS environment. Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers Show more Show less
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE Audits Business managers submissions of Budgets and validates Results Checks HR Feeds for changes in Plans, Employee details & updates records. Publishes data requested by the Sales teams, HR, Business managers, Finance. Finalises monthly accrual, forecasts, payments of the Sales incentives. Performs and secures approvals for the split searches, adjustments, Rep commission. Your Qualification & Experience Graduation degree with specialisation in Finance : BBA / MBA 3-5 years or prior experience in managing sales incentives. Skills Expert working knowledge of Excel and Power BI Excellent command over written and spoken English. Skills to perform and flourish in a GBS environment. Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Accountabilities and responsibilities Lead the design, implementation, and continuous improvement of end-to-end processes for TA services, ensuring consistency and efficiency of service levels. Work closely with HR, IT, and other departments to ensure processes for TA services are integrated into broader shared services operations. Act as the primary point of contact for processes for TA services-related issues and troubleshooting Oversee the use and management of Talent Acquisition systems and other digital platforms supporting TA Oversee the logistical tasks and activities to support the deployment of global learning and development programs Identify and implement innovative solutions and technologies to automate and enhance the learning experience and operational efficiency Ensure processes for TA services comply with organizational policies, legal requirements, and industry best practices Manage reporting frameworks and dashboards for learning activities, including mandatory training, performance metrics, and audit compliance Lead a team of TA support staff within the shared services model, providing guidance, mentoring, and performance feedback Foster a culture of continuous learning and process improvement within the team Monitor and manage the budget for TA shared services activities, ensuring cost-effective operations. Ensure high levels of service and support for employees and managers in their interaction with TA shared services. Experience requirements 14+yrs of overall experience and 5+ years SSC experience, preferably in TA with exposure to TA tech. Eightfold knowledge is a plus Experience in establishing TA services team and processes Experience working on process development, management and continuous improvement Experience in managing a team and working alongside multiple departments Experience in working with business leaders and stakeholders Knowledge & Skills requirements Ability to streamline and optimize learning operations Strong relationship management skills with stakeholders across multiple departments Proficiency in leveraging technology for process automation and service delivery. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Accountabilities And Responsibilities Lead the design, implementation, and continuous improvement of end-to-end processes for TA services, ensuring consistency and efficiency of service levels. Work closely with HR, IT, and other departments to ensure processes for TA services are integrated into broader shared services operations. Act as the primary point of contact for processes for TA services-related issues and troubleshooting Oversee the use and management of Talent Acquisition systems and other digital platforms supporting TA Oversee the logistical tasks and activities to support the deployment of global learning and development programs Identify and implement innovative solutions and technologies to automate and enhance the learning experience and operational efficiency Ensure processes for TA services comply with organizational policies, legal requirements, and industry best practices Manage reporting frameworks and dashboards for learning activities, including mandatory training, performance metrics, and audit compliance Lead a team of TA support staff within the shared services model, providing guidance, mentoring, and performance feedback Foster a culture of continuous learning and process improvement within the team Monitor and manage the budget for TA shared services activities, ensuring cost-effective operations. Ensure high levels of service and support for employees and managers in their interaction with TA shared services. Experience Requirements 14+yrs of overall experience and 5+ years SSC experience, preferably in TA with exposure to TA tech. Eightfold knowledge is a plus Experience in establishing TA services team and processes Experience working on process development, management and continuous improvement Experience in managing a team and working alongside multiple departments Experience in working with business leaders and stakeholders Knowledge & Skills Requirements Ability to streamline and optimize learning operations Strong relationship management skills with stakeholders across multiple departments Proficiency in leveraging technology for process automation and service delivery. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Accountabilities And Responsibilities Lead the design, implementation, and continuous improvement of end-to-end processes for L&D services, ensuring consistency and efficiency of service levels. Work closely with HR, IT, and other departments to ensure processes for L&D services are integrated into broader shared services operations. Act as the primary point of contact for processes for L&D services-related issues and troubleshooting Oversee the use and management of learning management systems (LMS) and other digital platforms supporting L&D Oversee the logistical tasks and activities to support the deployment of global learning and development programs Identify and implement innovative solutions and technologies to automate and enhance the learning experience and operational efficiency Ensure processes for L&D services comply with organizational policies, legal requirements, and industry best practices Manage reporting frameworks and dashboards for learning activities, including mandatory training, performance metrics, and audit compliance Lead a team of L&D support staff within the shared services model, providing guidance, mentoring, and performance feedback Foster a culture of continuous learning and process improvement within the team Monitor and manage the budget for L&D shared services activities, ensuring cost-effective operations. Ensure high levels of service and support for employees and managers in their interaction with L&D shared services. Experience Requirements 14+yrs of overall experience and 5+ years SSC experience, preferably in L&D with exposure to L&D tech Experience in establishing L&D services team and processes Experience working on process development, management and continuous improvement Experience in managing a team and working alongside multiple departments Experience in working with business leaders and stakeholders Knowledge & Skills Requirements Ability to streamline and optimize learning operations Strong relationship management skills with stakeholders across multiple departments Proficiency in leveraging technology for process automation and service delivery. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE Audits Business managers submissions of Budgets and validates Results Checks HR Feeds for changes in Plans, Employee details & updates records. Publishes data requested by the Sales teams, HR, Business managers, Finance. Finalises monthly accrual, forecasts, payments of the Sales incentives. Performs and secures approvals for the split searches, adjustments, Rep commission. Your Qualification & Experience Graduation degree with specialisation in Finance : BBA / MBA 3-5 years or prior experience in managing sales incentives. Skills Expert working knowledge of Excel and Power BI Excellent command over written and spoken English. Skills to perform and flourish in a GBS environment. Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE Audits Business managers submissions of Budgets and validates Results Checks HR Feeds for changes in Plans, Employee details & updates records. Publishes data requested by the Sales teams, HR, Business managers, Finance. Finalises monthly accrual, forecasts, payments of the Sales incentives. Performs and secures approvals for the split searches, adjustments, Rep commission. Your Qualification & Experience Graduation degree with specialisation in Finance : BBA / MBA 3-5 years or prior experience in managing sales incentives. Skills Expert working knowledge of Excel and Power BI Excellent command over written and spoken English. Skills to perform and flourish in a GBS environment. Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description: As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets. Responsibilities Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications. Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets. Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains. Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA). Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects. Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash. Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery. Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. Contribute to the innovation quotient of the team via Patents, Industry standard publications etc. Qualifications: Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience. Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture. Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems. Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis. Familiarity with formal verification techniques, static/dynamic power checks. Proficiency in scripting and automation using Python. Excellent leadership, communication skills. Experience working with global cross-functional teams. Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description: As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets. Responsibilities Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications. Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets. Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains. Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA). Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects. Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash. Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery. Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. Contribute to the innovation quotient of the team via Patents, Industry standard publications etc. Qualifications: Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience. Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture. Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems. Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis. Familiarity with formal verification techniques, static/dynamic power checks. Proficiency in scripting and automation using Python. Excellent leadership, communication skills. Experience working with global cross-functional teams. Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets. Responsibilities Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications. Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets. Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains. Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA). Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects. Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash. Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery. Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. Contribute to the innovation quotient of the team via Patents, Industry standard publications etc. Qualifications Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience. Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture. Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems. Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis. Familiarity with formal verification techniques, static/dynamic power checks. Proficiency in scripting and automation using Python. Excellent leadership, communication skills. Experience working with global cross-functional teams. Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE The Incumbent will be responsible for design Implementation (RTL2GDSII) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars. Responsibilities include guiding and reviewing work done by younger engineers along with being a strong technical contributor. This would involve strong communication and interpersonal skills , synthesizing and reporting data to management and customer. The job involve all aspects of Chip and IP Implementation using leading edge technologies like 7nm FINFET and 28FDSOI from RTL to GDSII. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements. YOUR SKILLS & EXPERIENCES Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) Strong in Reporting to management and customer Hands-on experience with synopsys OR Cadence PnR tools, Floorplanning, IR Drop and Physical verification Capable of working independently as well as technical lead Know-how of handling leading edge technologies like 16nm/7nm FIFET and 28FDSOI Strong communication and interpersonal skills Should have good understanding of verilog/VHDL Exposure to low power techniques Knowledge of tcl and perl scripting is a must Should have a strong sense of urgency Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description : Drive to “zero-defect”. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on standalone IPs, Subsystem level and SoC level. Responsibilities include but not limited: Verification planning, reviewing, architecture definition, Verification test bench development and implementation Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs. Development of direct and constrained-random stimulus, Understanding and analysis of RTL code, functional, assertion coverage results. Strong skills in debug, failure re-creation and root cause analysis Gate level simulations (unit delay, and with SDF annotated) and its debugging Test pattern debugging and testing for verification and automatic testers Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost effective and innovative verification techniques Assertion based verification and automated testcase/scenario generation (eg. Perspec) will be a plus Technical background/Key Skills: Qualification: Bachelors/Masters in Electronics/Computer Science VHDL/Verilog, System Verilog, C language OVM/UVM, Class based verification methodologies Deep Understanding of ARM multi core based SoC architecture AMBA – AXI, AHB, APB bus protocols NIC/FlexNOC interconnect architecture knowledge Indepth knowledge or ARM Based Core. Understanding of Trace and Debug infrastructure. Knowledge of memory controller and NVM will be a plus Scripting proficiency - PERL, Python, UNIX/LINUX Simulation tools like – Xcelium/VCS/Questasim. Perspec. Planning and regression tools like VManager Exposure to any of defect and version management tool Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE The Incumbent will be responsible for design Implementation (RTL2GDSII) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars. Responsibilities include guiding and reviewing work done by younger engineers along with being a strong technical contributor. This would involve strong communication and interpersonal skills , synthesizing and reporting data to management and customer. The job involve all aspects of Chip and IP Implementation using leading edge technologies like 7nm FINFET and 28FDSOI from RTL to GDSII. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements. YOUR SKILLS & EXPERIENCES Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) Strong in Reporting to management and customer Hands-on experience with synopsys OR Cadence PnR tools, Floorplanning, IR Drop and Physical verification Capable of working independently as well as technical lead Know-how of handling leading edge technologies like 16nm/7nm FIFET and 28FDSOI Strong communication and interpersonal skills Should have good understanding of verilog/VHDL Exposure to low power techniques Knowledge of tcl and perl scripting is a must Should have a strong sense of urgency Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE The Incumbent will be responsible for design Implementation (RTL2GDSII) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars. Responsibilities include guiding and reviewing work done by younger engineers along with being a strong technical contributor. This would involve strong communication and interpersonal skills , synthesizing and reporting data to management and customer. The job involve all aspects of Chip and IP Implementation using leading edge technologies like 7nm FINFET and 28FDSOI from RTL to GDSII. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements. Your Skills & Experiences Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) Strong in Reporting to management and customer Hands-on experience with synopsys OR Cadence PnR tools, Floorplanning, IR Drop and Physical verification Capable of working independently as well as technical lead Know-how of handling leading edge technologies like 16nm/7nm FIFET and 28FDSOI Strong communication and interpersonal skills Should have good understanding of verilog/VHDL Exposure to low power techniques Knowledge of tcl and perl scripting is a must Should have a strong sense of urgency Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. YOUR ROLE The Incumbent will be responsible for design Implementation (RTL2GDSII) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars. Responsibilities include guiding and reviewing work done by younger engineers along with being a strong technical contributor. This would involve strong communication and interpersonal skills , synthesizing and reporting data to management and customer. The job involve all aspects of Chip and IP Implementation using leading edge technologies like 7nm FINFET and 28FDSOI from RTL to GDSII. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements. Your Skills & Experiences Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop ) Strong in Reporting to management and customer Hands-on experience with synopsys OR Cadence PnR tools, Floorplanning, IR Drop and Physical verification Capable of working independently as well as technical lead Know-how of handling leading edge technologies like 16nm/7nm FIFET and 28FDSOI Strong communication and interpersonal skills Should have good understanding of verilog/VHDL Exposure to low power techniques Knowledge of tcl and perl scripting is a must Should have a strong sense of urgency Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description Drive to “zero-defect”. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on standalone IPs, Subsystem level and SoC level. Responsibilities Include But Not Limited Verification planning, reviewing, architecture definition, Verification test bench development and implementation Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs. Development of direct and constrained-random stimulus, Understanding and analysis of RTL code, functional, assertion coverage results. Strong skills in debug, failure re-creation and root cause analysis Gate level simulations (unit delay, and with SDF annotated) and its debugging Test pattern debugging and testing for verification and automatic testers Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost effective and innovative verification techniques Assertion based verification and automated testcase/scenario generation (eg. Perspec) will be a plus Technical Background/Key Skills Qualification: Bachelors/Masters in Electronics/Computer Science VHDL/Verilog, System Verilog, C language OVM/UVM, Class based verification methodologies Deep Understanding of ARM multi core based SoC architecture AMBA – AXI, AHB, APB bus protocols NIC/FlexNOC interconnect architecture knowledge Indepth knowledge or ARM Based Core. Understanding of Trace and Debug infrastructure. Knowledge of memory controller and NVM will be a plus Scripting proficiency - PERL, Python, UNIX/LINUX Simulation tools like – Xcelium/VCS/Questasim. Perspec. Planning and regression tools like VManager Exposure to any of defect and version management tool Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Roles : Chip Lead / SoC Design Leader / Timing Constraints Lead Job Description SoC design leader with extensive experience(10-15 years) and proven track record in SoC/full-chip micro architecture and design with solid focus on delivering the products across various tech nodes. Individual should have very good hold on SoC global specs and functionalities like core, platforms, clock, reset & power, etc. Must have good understanding on adjoining SoC implementation functions like functional verification, DFT, physical implementation, timing analysis, pre & post-Si validation, test and product engineering etc. The SoC lead will be closely working and collaborating with systems teams and driving RTL design teams for specification development of IP’s, complex subsystems, and chip-top - taking the design from spec definition to RTL development and integration, through entire RTL2GDS flow. In this role candidate will be responsible for overall chip development schedule and project plans, while being able to evaluate technical challenges and concepts and associated risks, challenging and negotiating different functions for seamless and most efficient development cycle while granting right quality deliverables. Design lead will also coordinate with multiple teams like analog IP team, foundation IP’s and libraries team for I/O’s, memories etc. incl 3rd party vendors, digital IP team to define and build block specifications, deliverables, collaterals etc. Alongwith RTL, the candidate has also to ensure the collaterals related to timing constraints for the corresponding RTL, ensuring its formal/structural verification performed. Responsibilities Include But Not Limited To Drive architecture & application teams in converging to an optimal specification from performance, design effort/cost point of view. This includes detailed technical discussions and evaluations on IP choices and specifications, SoC architecture definitions covering different core and memory subsystems, solutions for clocking, power management, interconnect etc with target of PPA optimization to grant a competitive balance between product features and time-to-market. Close engagement with systems teams and customer interfaces to enable correct design decisions while working to build and develop system level knowledge within the design team. Conducts analyses covering feasibility studies, risk analysis, power, die size estimation etc. Drive design implementation functions including sub-groups for RTL development and top integration, verification, performance evaluation and pre-Si validation, DFT, physical implementation team for execution of entire RTL2GDS flow. Running weekly reviews of open issues across development functions, closely monitoring and tracking, and provide technical leadership to individuals from outside the function and owning the outcome of the project Manage project-related activities like design team meetings, project status reporting, project reviews in compliance with product development lifecycle. Collaborates with the teams across project core team members like engineering, validation, packaging, quality & reliability, marketing etc. Technical Skills/background Qualification: Bachelors/Masters in Electronics/Electrical Engineering Experienced about system applications on aspects related to architectural choices in order to optimize for device performance, power and area. Good knowledge and understanding of advanced ARM real time and application CPU cores and memory subsystems, system bus architectures (like AHB/AXI), Arteris NOC and other interconnect technologies, debug subsystems, critical aspects like SoC clocking, reset and power mgmt., high speed SerDes, analog integration, RTL design and SoC integration with multiple asynchronous clock domains, bottlenecks identification, timing issues anticipation and resolution. Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues for high frequency designs. Design experience in mid-high complexity product developments in FDSOI 28nm, 16 FFC, 7nm technology nodes. Knowledge of Automotive Functional Safety ISO26262 is a plus. Leadership Skills Proven track record of leadership role in managing high level complex designs, driving and coordinating across different teams. Good negotiator and able to manage tough situations. Adaptability to align and balance resources & time constraints according to business need. Should possess strong communication skills to ensure effective interaction both with Management and internal project/design sub-groups members Good interpersonal skills. Provide direction, mentoring, and leadership to small to medium-sized technical groups. Footer for Internal Candidates Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers Same Posting Description for Internal and External Candidates Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers
Role Overview: As a member of ST, you will be contributing to the design Implementation (RTL2GDSII) of products related to Engine control, Safety (including airbag), Body, Chassis, and Advanced Driver Assistance System (ADAS) for futuristic cars. You will be responsible for guiding and reviewing the work done by younger engineers, as well as being a strong technical contributor. This role requires strong communication and interpersonal skills for synthesizing and reporting data to management and customers. You will be working on Chip and IP Implementation using cutting-edge technologies like 7nm FINFET and 28FDSOI, from RTL to GDSII. Constantly challenged to meet automotive standards while closing design requirements. Key Responsibilities: - Knowledge of full RTL to GDSII flow (Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop) - Strong in reporting to management and customers - Hands-on experience with Synopsys or Cadence PnR tools, Floorplanning, IR Drop, and Physical verification - Capable of working independently as well as a technical lead - Knowledge of handling leading-edge technologies like 16nm/7nm FINFET and 28FDSOI - Strong communication and interpersonal skills - Good understanding of Verilog/VHDL - Exposure to low power techniques - Knowledge of TCL and Perl scripting is a must - Strong sense of urgency Qualifications Required: - Hands-on experience in design Implementation (RTL2GDSII) of automotive products - Proficiency in working with advanced technologies like 7nm FINFET and 28FDSOI - Strong communication and interpersonal skills for effective collaboration - Knowledge of Verilog/VHDL and low power techniques - Experience with Synopsys or Cadence PnR tools, Floorplanning, IR Drop, and Physical verification - Familiarity with TCL and Perl scripting - Ability to work independently and as a technical lead Join ST to be part of a global business with diverse and dedicated creators, working towards a smarter, greener, and more sustainable future. Your contribution will drive innovation and make a positive impact on society. Visit st.com/careers to explore more opportunities.,