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Cadence Design Systems
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Sr Principal RTL Design Engineer

Sr Principal RTL Design Engineer

Cadence Design Systems

12 - 16 years

0 Lacs

karnataka

Posted:5 days ago| Platform: Shine logo

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Skills Required

asic design verilog coding rtl design pcie usb ethernet sata lint sdc cdc lec ucie mipidphy hdmidisplay rtl checks synthesis flow timing constraints verilog testbench simulations

Work Mode

On-site

Job Type

Full Time

Job Description

As an ASIC Design Engineer at Cadence, you will be responsible for: - Having 12+ years of experience in ASIC design - Being proficient in Verilog coding, RTL design, and complex control path and data path designs - Having knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA - Knowing RTL checks like LINT, SDC, CDC, synthesis flow, LEC, and timing constraints - Experience in writing Verilog testbench and running simulations You will be part of a team that is working on impactful technology solutions, pushing boundaries, and solving challenges that others cannot.,

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Sr Principal RTL Design Engineer