29 Sdc Jobs

As an ASIC Design Engineer at Cadence, you will be responsible for: - Having 12+ years of experience in ASIC design - Being proficient in Verilog coding, RTL design, and complex control path and data path designs - Having knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA - Knowing RTL checks like LINT, SDC, CDC, synthesis flow, LEC, and timing constraints - Experience in writing Verilog testbench and running simulations You will be part of a team that is working on impactful technology solutions, pushing boundaries, and solving challenges that others cannot.,

As an experienced digital design engineer at Terminus Circuits, your role will involve a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. Your primary responsibility will be to design and verify RTL code for high-speed SerDes-related digital blocks. You must have excellent verbal and written communication skills to effectively collaborate with the team. Key Responsibilities: - Design and verify RTL code for high-speed SerDes-related digital blocks - Synthesize complex SoCs block/top level and write timing constraints - Conduct formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints - Perform post-layout STA closure and timing ECOs - Work on...

Position: Senior FPGA Engineer Company: izmo Microsystems Ltd. Location: Whitefield, Bangalore ## Only Immediate Joiners ## izmo Microsystems (www.izmomicro.com) is a leading semiconductor and systems company based in Bangalore, specializing in advanced System-in-Package (SiP), silicon photonics packaging, and high-speed interconnect solutions. Backed by deep expertise in 3D packaging and photonic integration, we also design complete embedded and FPGA-based system platforms for data centers, telecom, automotive, and intelligent devices. We combine proven capability with innovation to power next-generation electronic systems. Job Summary: We are seeking a highly skilled Senior FPGA Engineer w...

Experince 3 years in enterprise infrastructure with hands-on Dell PowerFlex Rack experience. Skilled in PowerFlex architecture, VMware ESXi upgrades, firmware and BIOS management, CIFS/NFS sharing, and strong in troubleshooting and communication. Required Candidate profile Powerflex In-depth Experince VMWARE In-Depth Hands-on Exposure (Upgrades 7.x & above) DELL PowerEdge Servers Ability to interpret Dell RCM documentation and Intelligent Catalogs for upgrade planning.

Altera is seeking highly skilled Senior/Lead FPGA Silicon Design Engineer to ensure the excellence of next-generation Ethernet/Transceiver/Crypto for top-tier FPGAs. This role offers opportunity to make a significant impact at a tech-driven company that provides leading programmable solutions, easily deployable in applications ranging from embedded, industrial, & cloud to edge, unlocking limitless possibilities Responsibilities: Develop Micro-architecture and Design implementation for Ethernet/Transceiver/Crypto IPs and subsystems. Work closely with the Architects to come up with an optimal design, RTL code development, involvement in pre-silicon and post-silicon debug, and own all the front...

As a Static Timing Analysis (STA) Engineer at the company in Singapore, you will play a crucial role in the SoC design team, focusing on timing signoff and analysis of cutting-edge IPs and chips in advanced process nodes. Your expertise in using Synopsys NanoTime or similar tools will be essential for the success of the projects. Key Responsibilities: - Perform full-chip and block-level Static Timing Analysis using NanoTime - Collaborate with physical design and RTL teams to ensure timing closure - Apply timing constraints and execute timing ECOs as necessary - Run timing analysis across various PVT corners and modes - Provide support for design sign-off activities such as STA, SI, cross-tal...

As an ASIC SOC RTL Design Lead/Architect at Eximietas Design, you will be responsible for driving the development of cutting-edge solutions in the VLSI domain. Your role will involve collaborating with architects, verification teams, and customer leads to ensure the successful delivery of projects. **Key Responsibilities:** - Collaborate with architects, pre- and post-silicon verification teams to meet deadlines. - Coordinate with customer leads to ensure timely delivery of all project deliverables. **Qualifications Required:** - Bachelor's degree in Computer Science, Electrical/Electronics with a minimum of 10 years of ASIC SOC RTL (Micro-architecture) experience. - ARM Processor Integratio...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER(Timing Constraints/STA Signoff Technical Lead) The Role As a m...

Job Title/Designation: Senior Devops Engineer Employment Type: Full Time, Permanent- WFO Job Description: Roles and Responsibilities Hands on experience of continuous integration, continuous delivery, automated testing and all phases of the Software Development Life Cycle Expert in Source Control Management, including branching, integration, and merging techniques Experience performing integrations for production builds and server hot fixes Experience with Application Lifecycle Management tools and Source Control systems, such as GIT, Azure DevOps/VSTS Hands-on experience in setting up DevOps pipeline for a project (Automated deployments with Continuous Integration/Delivery workflows) Experi...

SDC and constraints syntax Timing signoff tools like Primetime / Tempus is a must MMMC, DMSA or Tweaker Block /SOC,AOCV/POCV, TCL / Perl.

As a DFT Lead, you will be responsible for defining, developing, and implementing Design-For-Test (DFT) methodologies for high-performance LiDAR SoCs. You will own DFT planning, insertion, verification, and validation, and collaborate with RTL, Physical Design, IP vendors, and ASIC partners to ensure proper DFT implementation. The role includes supporting post-silicon bring-up, silicon debug, yield improvement, and creating/maintaining documentation and DFT guidelines. You will ensure robust test strategies for automotive-grade SoCs with focus on reliability, quality, and compliance. Location-Remote, Delhi NCR, Bangalore, Chennai, Pune, Kolkata, Ahmedabad, Mumbai, Hyderabad

As a Senior ASIC CAD/EDA Engineer in the VLSI/Semiconductor Industry, your role involves deploying and supporting front-end tools, developing scripts for automation, working closely with design, implementation, and verification teams. You will be responsible for: - Deploying and supporting front-end tools like RTL simulators, low power tools, static RTL checkers, and formal verification tools - Developing scripts to automate regression and debug flows, enabling CI/CD - Streamlining compute infrastructure utilization using load distribution tools - Identifying and prioritizing internal user needs and developing capabilities for them - Integrating tools, repos, and compute infrastructure using...

Role & responsibilities Develop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.). Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG). Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure requirements. Work with synthesis, P&R, and STA teams to merge functional and test-mode constraints consistently. Debug timing violations across functional and DFT modes, and propose fixes (false paths, multicycle paths, case analysis, test clocks). Ensure SDC quality by writing scripts/checkers for constraint consistency, redundancy, and c...

You will be joining a dynamic and energetic team at Lattice, a global community of engineers, designers, and manufacturing operations specialists. Together with our world-class sales, marketing, and support teams, we are dedicated to developing cutting-edge programmable logic solutions that are revolutionizing the industry. Our core values revolve around research and development, product innovation, and exceptional customer service, which we deliver with unwavering commitment and a strong competitive drive. As a qualified candidate for the position based in Pune, India, you will play a crucial role in FPGA projects within the region. Your expertise in RTL design, coding best practices, algor...

Crane Worldwide Logistics is a leader in supply chain solutions with over 130 locations across 30 countries providing individual services that address clients" logistics challenges. As an Air Export specialist, your primary responsibilities will include handling daily Air Export shipments and their operations. This involves creating jobs in TMF for each shipment before execution, following up with CHA and transporter, maintaining daily planning for shipments, accruing all vendor costs at house & Master level, sending billing instructions to the billing desk within agreed TAT, updating and maintaining shipment DSR on a daily basis, dispatching all invoices to the shipper as per agreed SOP, ma...

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges tha...

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

You are a highly skilled and motivated Senior CAD Engineer responsible for supporting and enhancing the front-end EDA infrastructure. Your expertise in CAD tools, scripting, and ASIC design flows will be instrumental in developing efficient and scalable methodologies for large-scale silicon projects. Your key responsibilities will include deploying and supporting front-end EDA tools such as RTL simulators, static checkers, and formal verification tools. You will be required to develop automation scripts for regression and debug flows, administer and optimize Linux-based compute infrastructure, and collaborate with internal teams to identify CAD needs and deliver tailored solutions. Additiona...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 3 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Collaboration with...

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System ...

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualificati...

Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are currently looking to hire Senior ASIC SOC RTL Design Leads with a minimum of 10 years of experience in the field. The preferred locations for this position are Visakhapatnam or Bangalore. The ideal candidate should possess a Bachelor's degree in Computer Science or Electrical/Electronics with a strong background in ASIC SOC RTL (Micro-architecture). Knowledge and experience in ARM Processor Integration, particularly M55, is highly desirable. In addition, the candidate should have a solid understanding of design concepts, ASIC ...

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL de...

Collaborate with customers to ensure Synopsys SDC Constraints solutions meet expectations and use cases Develop and integrate design methodologies with broader Synopsys toolsets Track customer engagements, priorities, and communicate effectively with Marketing and Upper Management Prepare and deliver technical presentations and training to customers and Field Application Engineers (FAEs) Routinely gather customer feedback to influence internal product roadmap and R&D prioritization Provide technical direction to R&D and champion critical customer-driven enhancements The Impact You Will Have: Increase customer satisfaction through tailored SDC solutions Strengthen product integration and ecos...

- Experience with SDC assembly - violations from timing reports and develop strategies for improvement [Tools] PrimeTime @ Synopsys - Tempus @ Cadence [Good to have] - Able to understand DC and AC characteristics listed in device datasheets