17 Sdc Jobs

Role & responsibilities Develop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.). Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG). Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure requirements. Work with synthesis, P&R, and STA teams to merge functional and test-mode constraints consistently. Debug timing violations across functional and DFT modes, and propose fixes (false paths, multicycle paths, case analysis, test clocks). Ensure SDC quality by writing scripts/checkers for constraint consistency, redundancy, and c...

You will be joining a dynamic and energetic team at Lattice, a global community of engineers, designers, and manufacturing operations specialists. Together with our world-class sales, marketing, and support teams, we are dedicated to developing cutting-edge programmable logic solutions that are revolutionizing the industry. Our core values revolve around research and development, product innovation, and exceptional customer service, which we deliver with unwavering commitment and a strong competitive drive. As a qualified candidate for the position based in Pune, India, you will play a crucial role in FPGA projects within the region. Your expertise in RTL design, coding best practices, algor...

Crane Worldwide Logistics is a leader in supply chain solutions with over 130 locations across 30 countries providing individual services that address clients" logistics challenges. As an Air Export specialist, your primary responsibilities will include handling daily Air Export shipments and their operations. This involves creating jobs in TMF for each shipment before execution, following up with CHA and transporter, maintaining daily planning for shipments, accruing all vendor costs at house & Master level, sending billing instructions to the billing desk within agreed TAT, updating and maintaining shipment DSR on a daily basis, dispatching all invoices to the shipper as per agreed SOP, ma...

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges tha...

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

You are a highly skilled and motivated Senior CAD Engineer responsible for supporting and enhancing the front-end EDA infrastructure. Your expertise in CAD tools, scripting, and ASIC design flows will be instrumental in developing efficient and scalable methodologies for large-scale silicon projects. Your key responsibilities will include deploying and supporting front-end EDA tools such as RTL simulators, static checkers, and formal verification tools. You will be required to develop automation scripts for regression and debug flows, administer and optimize Linux-based compute infrastructure, and collaborate with internal teams to identify CAD needs and deliver tailored solutions. Additiona...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 3 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Collaboration with...

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System ...

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualificati...

Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are currently looking to hire Senior ASIC SOC RTL Design Leads with a minimum of 10 years of experience in the field. The preferred locations for this position are Visakhapatnam or Bangalore. The ideal candidate should possess a Bachelor's degree in Computer Science or Electrical/Electronics with a strong background in ASIC SOC RTL (Micro-architecture). Knowledge and experience in ARM Processor Integration, particularly M55, is highly desirable. In addition, the candidate should have a solid understanding of design concepts, ASIC ...

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL de...

Collaborate with customers to ensure Synopsys SDC Constraints solutions meet expectations and use cases Develop and integrate design methodologies with broader Synopsys toolsets Track customer engagements, priorities, and communicate effectively with Marketing and Upper Management Prepare and deliver technical presentations and training to customers and Field Application Engineers (FAEs) Routinely gather customer feedback to influence internal product roadmap and R&D prioritization Provide technical direction to R&D and champion critical customer-driven enhancements The Impact You Will Have: Increase customer satisfaction through tailored SDC solutions Strengthen product integration and ecos...

- Experience with SDC assembly - violations from timing reports and develop strategies for improvement [Tools] PrimeTime @ Synopsys - Tempus @ Cadence [Good to have] - Able to understand DC and AC characteristics listed in device datasheets

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

Greetings from Quest Global Please find the details and kindly send me your Profile . RTL Design 10-15 Years Location : Bangalore/Hyderabad 1. Should have worked on ASIC/SOC projects using 22nm or smaller technology node 2. Expertise in automated RTL Integration using any of the industry standard tool/EDA flow 3. Expertise in SDC and UPF constraints development and checking 4. Expertise in Timing violation debug/fix at netlist level 5. Good knowledge on AHB/AXI/APB/PIPE interface 6. Expertise in Lint, CDC and VCLP, Synthesis, LEC 7. Very Strong in Python and TCL scripting • Nice to have skills: 8. Exposure to PCIe/Ucie 9. Experience in Leading small rtl design team • Location: Bangalore and ...

Role & responsibilities We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimiza...