13 Ucie Jobs

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

• Working experience in IP/ASIC/ SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Role & responsibilities Preferred candidate profile

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

KEY EXPERTISE : - Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. - Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. - Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. - Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. - Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. - Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. - Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). - Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. - Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. - Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. - Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. - Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. - Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. - Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. - Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. - Good Team Player : Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. - Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .

- Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA). - Should be excellent in DDR protocol knowledge. - Must be an expert in micro architecture and RTL coding. Skill set needed - Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.) Scripting : (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up. What You'll Do: - You will be responsible for pre-sales support, proposing architecture to customers based on their requirements. - You will work with team to come up with architecture and micro-architecture and work with cross functional team to ensure delivery - You will manage the design / RTL team to achieve the project goals - You will work with customer, provide technical support and provide collaterals agreed upon - You will work with team to achieve flow, methodology improvements to achieve high reuse - You will work with IP vendors to generate / get right configurations of the IP - You will manage team work allocation, schedule, risk mitigation and deliverables from design team. What You'll Need: - 4+ Years of experience in understanding of ARM based architecture, CPU subsystems, interconnect, boot process, memory subsystem, knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks - Good understanding of IPs, integration/application requirement, work with RTL team/vendors to achieve architecture goals - Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe, DDRx, USB, SATA, . - Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect solutions available - Should have good understanding of process / flow to achieve power & performance goals - Should understand and work on all aspects of VLSI development from SoC architecture, micro architecture, RTL coding, RTL quality checks, silicon bring up. - Should have good understanding of requirements from physical design, FPGA, Software, DFT and verification team. - Should have handled a design from Spec to GDS-II - Track design progress, working with cross functional teams, delivering on agreed upon milestones. - Should provide mentoring and support to the team

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

- Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA). - Should be excellent in DDR protocol knowledge. - Must be an expert in micro architecture and RTL coding. Skill set needed - Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.) Scripting : (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up. What You'll Do: - You will be responsible for pre-sales support, proposing architecture to customers based on their requirements. - You will work with team to come up with architecture and micro-architecture and work with cross functional team to ensure delivery - You will manage the design / RTL team to achieve the project goals - You will work with customer, provide technical support and provide collaterals agreed upon - You will work with team to achieve flow, methodology improvements to achieve high reuse - You will work with IP vendors to generate / get right configurations of the IP - You will manage team work allocation, schedule, risk mitigation and deliverables from design team. What You'll Need: - 4+ Years of experience in understanding of ARM based architecture, CPU subsystems, interconnect, boot process, memory subsystem, knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks - Good understanding of IPs, integration/application requirement, work with RTL team/vendors to achieve architecture goals - Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe, DDRx, USB, SATA, . - Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect solutions available - Should have good understanding of process / flow to achieve power & performance goals - Should understand and work on all aspects of VLSI development from SoC architecture, micro architecture, RTL coding, RTL quality checks, silicon bring up. - Should have good understanding of requirements from physical design, FPGA, Software, DFT and verification team. - Should have handled a design from Spec to GDS-II - Track design progress, working with cross functional teams, delivering on agreed upon milestones. - Should provide mentoring and support to the team

Job Title: RTL Design Verification Lead & Manager Location: Bangalore Job Type: Full-Time Payroll: Direct Payroll Experience: 6 to 12 Years Work Mode: Work From Office Interview Mode: Virtual Interview Notice Period: 0-30 days preferred For Manager roles, a minimum of 8+ years of relevant RTL verification experience is required. Job Summary: We are looking for highly skilled RTL Verification Leads and Managers to join our motivated verification team. The selected candidates will play key roles in IP verification, with a focus on protocols such as UCIe, HBM, PCIe, AXI/ACE, Ethernet, DDR, and more. This position requires deep expertise in advanced verification methodologies and a strong background in RTL verification. Key Responsibilities: Lead and execute RTL verification tasks for IPs like UCIe, HBM, PCIe, and Bus Logic. Implement advanced verification methodologies such as UVM/OVM/VMM/SystemVerilog. Generate constrained random stimulus and perform assertion-based verification and functional coverage. Oversee register verification standards and manage NLP/GLS verification flows. Conduct IP and sub-system level verification for protocols including PCIe, UCIe, and HBM. Facilitate controller interoperability testing at the sub-system level. Qualifications: BE/ME/MTech/MS in Electrical Engineering or a related field. 6 to 12 years of RTL verification experience. Proficiency in UVM/OVM/VMM/SystemVerilog. Strong knowledge of constrained random stimulus generation, assertion-based verification, and functional coverage techniques. Experience with register verification standards and NLP/GLS verification flows. Hands-on experience in IP and sub-system level verification for protocols like PCIe, UCIe, and HBM is a strong plus. Prior experience in controller interoperability testing at the sub-system level is desirable. Note: Note: We are aiming to close this requirement soon so preference will be given to candidates who can join quickly.

Design Verification Engineer In-House ODC Project We are looking for an experienced Design Verification Engineer to be part of our in-house ODC project . The ideal candidate will be an individual contributor with expertise in SoC, Subsystem, or IP verification using high-speed serial protocols and advanced protocols . The candidate should have a strong command of SystemVerilog (SV) and UVM , including writing test cases, sequences, OOPs concepts, and UPF implementation . The role requires hands-on experience in scratch-level work , ensuring verification coverage from the ground up. Experience: 4 to 20+ years Location: Bangalore, Chennai, Pune Notice Period: Immediate to 30 days If you're ready to take on challenging verification tasks and contribute to cutting-edge projects, apply now!

We are seeking a UCIE Design/Verification Engineer to drive the development and validation of next-generation chiplet-based interconnect solutions.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/System Verilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields. 4-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment. Preferred Skills : Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O. Prior experience working with large, cross-functional teams and managing design schedules. Experience with software tools for RTL analysis and optimization. Hands-on experience in leading ASIC projects from specification to production. Perks and benefits According to company norms

Hiring: SoC (System-on-Chip) Architect / MCU (Microcontrollers) Architect Location: Noida & Hyderabad Experience: 10-25 years Work Mode: Hybrid (3 days in office) We are seeking an experienced SoC or MCU architect to join our team. This role presents an exciting opportunity to drive innovation in high-performance SoCs and MCUs while collaborating with cross-functional teams to define and implement cutting-edge semiconductor solutions. Key Responsibilities: Define and develop SoC/MCU architecture, translating product requirements into detailed technical specifications. Lead chip implementation, ensuring product compliance through verification, validation, characterization, and testing. Drive automotive SoC/MCU development with expertise in high-performance SoCs, vehicle computers, software-defined vehicles (SDVs), and MCUs. Optimize execution strategies by improving team structures, methodologies, and tools for enhanced efficiency and quality. Evaluate and make strategic decisions on IP selection, including make-versus-buy analysis. Collaborate with system architects, SoC design teams, software engineers, and business leaders to establish common methodologies and best practices. Engage with external stakeholders, manage supplier relationships, participate in technical conferences, and contribute to industry standards. Develop and implement training programs, ensuring the dissemination of best practices and lessons learned. Apply Now! Click on the Apply button or share your resume with Heena at heena.k@randstad.in Tag your connections who might be interested! Join us and shape the future of semiconductor technology!