28 Ucie Jobs

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day. JOB Responsilibilities: BE/BTECH/ME/MTECH The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips. What we do : . Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators. . Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team) . Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet. . Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release. . Engage in interop and Customer Debug. What you'll gain : . Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's. . Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration. . Hardware and Subsystem design expertise. . Experience in deploying and debugging your Solutions in different customer environments. What we are looking for : Minimum Qualifications: . 10-15 years (with Btech) or 10 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. . 2-3 years of management experience leading/mentoring a small team of engineers . Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet. . Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Preferred Qualifications: . Experience leading System testing efforts for SERDES solutions. . Experience in PCIe/UCIe LTSSM states is a plus. . 1-2 years of experience in FPGA Design and Schematic design. . 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus. . Familiarity with Verilog RTL coding for FPGA, python,C/C++ . Good communication skills Seasoned Systems Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Juniors We're doing work that matters. Help us solve what others can't.

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, you will be involved in utilizing industry-standard protocols and methodologies. Your proficiency in System Verilog and Verilog, along with a solid understanding of Object Oriented Programming, will be essential for this role. As a Senior/Lead ASIC Verification Engineer, you will have the opportunity to lead the development of reusable Verification environments for a minimum of 2 projects using VMM, OVM, or UVM methodologies. Your expertise in protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocol will be valuable. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development updates, and collaborating with Architects and methodology experts to address issues and enhance output from an architecture/methodology perspective. If you are a proactive and reliable professional with a passion for Verification, we encourage you to share your updated CV with us at taufiq@synopsys.com or refer individuals who would be interested in this opportunity. At Synopsys, we value and promote Inclusion and Diversity, and we welcome applicants from diverse backgrounds without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,

You are looking for Analog Mixed Signal Designers to join our team and work on designing building blocks for high-speed IPs such as DDR, LPDDR, HBM, UCIe, and PCIe. As a member of our team, your responsibilities will include deriving circuit block level specifications from top-level specifications, designing optimized transistor-level analog and custom digital blocks, conducting Spice simulations to meet detailed specifications, guiding layout design for optimal performance, matching, and power delivery, performing performance characterization of designs in various conditions including reliability checks, and generating/delivering behavioral, timing, and physical models of circuits. You will also be involved in conducting design reviews at different phases of the design process. To be successful in this role, you should have a BE/M-Tech degree in Electrical & Electronics, strong fundamentals in RLC circuits, CMOS devices, digital design building blocks, and prior experience with custom design environments and spice simulators. A collaborative and positive attitude is essential for working effectively in our team. Depending on your experience level, you will be designated as a Design Team Member (0-4 years), a Technical Lead/Mentor (4-7 years), or a Team Lead/Manager (7+ years). Some example designs you may work on include Wireline channel transmitters, receivers, equalization circuits, serializers, deserializers, bandgap references, PLLs, DLLs, phase interpolators, comparators, DACs, and ADCs. Joining our team will provide you with opportunities for growth and learning, including close collaboration with experienced mentors and exposure to advanced process technologies such as 12nm, 7nm, 5nm, 3nm, and 2nm. We offer a fast-paced environment for high-performance individuals who are ready to take on challenges and advance their careers. If you are interested in this fantastic opportunity, please reach out to poojakarve@arf-design.com to learn more.,

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges that others find insurmountable.,

You will be joining 7Rays Semiconductors, a company that specializes in providing end-to-end VLSI design solutions to help clients achieve execution excellence. The team of experts at 7Rays Semiconductors focuses on architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using cutting-edge technologies and methodologies. Building effective partnerships with clients, the company delivers high-quality solutions tailored to meet specific needs, showcasing a commitment to excellence and innovation in semiconductor design. Located in Bangalore, KA, this opportunity requires a minimum of 5 years of experience in the Emulation domain. As an Emulation Engineer/Validation Engineer, your responsibilities will include building emulation models from RTL for IP/SS or SOC, bringing up emulation models, developing content, and collaborating with RTL designers and Verification engineers to resolve emulation build issues. You will also work closely with customers to address emulation challenges and partner with vendors to resolve emulation build issues. Ideal candidates should hold a B.Tech/M.Tech in Electronics/VLSI or equivalent and be familiar with SV/UVM methodology. Candidates should have hands-on experience with Emulators such as Palladium, Veloce, Zebu, etc., and demonstrate proficiency in porting ASIC RTL on the Emulators and generating Emulation builds. Additionally, expertise in domains/functions including AXI, APB, AHB, SPI, I2C, UART, PCIe, USB, Ethernet, CXL, Ucie, C2C, D2D, DDR4/5/6, LPDDR3/4/5/6, and NoC/Interconnect verification is required. Desired activities that candidates should be involved in are HW-SW co-verification, Boot, Reset, Clock verification, Low Power Verification, Regression management and debug, as well as the development of Scoreboard, Checkers, and tracker. Proficiency in scripting languages like PERL and PYTHON is also beneficial for this role.,

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years of hands-on DV experience in SystemVerilog/UVM, you will be responsible for owning and driving the verification of a block/subsystem or a SOC. An ideal candidate should have a proven track record of leading a team of engineers and possess extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Proficiency in Tesplan and Testbench development, execution of test plans using high-quality constrained random UVM tests to achieve coverage goals on time, and adeptness in debugging and exposure to all aspects of verification flow including Gatesims are essential. The candidate must have extensive experience in the verification of technologies such as PCI Express or UCIe, CXL or NVMe, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM, ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages, and Power Aware Simulations using UPF. Experience in using EDA tools like VCS, Verdi, Cadence Xcelium, Simvision, Jasper, and revision control systems such as Git, Perforce, Clearcase is required. Experience in SVA and formal verification is desirable, and knowledge of script development using Python, Perl, or TCL is an added advantage. The position is available in various locations including Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, and Pune. The ideal candidate must have a minimum of 7 years of YoE. Key Responsibilities: - Define product requirements and implement VLSI and hardware devices - Continuously upgrade and update design tools and frameworks - Analyze and select the right components and hardware elements for product engineering - Conduct cost-benefit analysis to choose the best design - Develop architectural designs for new and existing products - Implement derived solutions and troubleshoot critical problems - Evangelize architecture to project and customer teams to achieve the final solution - Monitor product solution and make continuous improvements - Understand market-driven business needs and technology trends to define architecture requirements and strategy - Develop Proof of Concepts (POCs) to demonstrate product feasibility - Provide solutioning for RFPs from clients and ensure overall product design assurance - Collaborate with sales, development, and consulting teams to reconcile solutions to architecture - Provide technical leadership in designing custom solutions using modern technology - Validate solutions from technology, cost structure, and customer differentiation perspectives - Identify and resolve problem areas in architectural design and solutions - Monitor industry and application trends and provide strategic input during product deployment - Support delivery team in product deployment and issue resolution - Develop product validation and performance testing plan in alignment with business requirements - Maintain product roadmap and provide inputs for product upgrades based on market needs - Build competencies and branding through necessary trainings, certifications, and Thought leadership content development - Mentor developers, designers, and junior architects for career enhancement - Contribute to the architecture practice by conducting selection interviews Performance Parameters: - Product design, engineering, and implementation: Measure based on CSAT, quality of design/architecture, FTR, delivery as per cost, quality, and timeline, POC review and standards - Capability development: Measure based on % of trainings and certifications completed, mentorship of technical teams, and development of Thought leadership content Wipro is dedicated to reinventing your world by building a modern, end-to-end digital transformation partner with ambitious goals. The company is looking for individuals who are inspired by reinvention and are committed to constant evolution in their careers and skills. Join Wipro to realize your ambitions and be part of a purpose-driven business that empowers you to design your own reinvention. Applications from people with disabilities are explicitly welcome.,

M. Tech candidates with 1+ years of experience in designverification systemverilog C++ protocols ideally UCIe CXL MIPI PCIe CHI etc. Role: Software Engineer II Location: Noida Notice Period: 15-30 days Job Descriptions: • M. Tech with 1+ Year of relevant experience in functional verification, test environment creation using SV/UVM with strong debug skills. • Hands-on knowledge of C/C++/Scripting. • Working experience on layered Protocols - UCIe, PCIe, CXL, Ethernet. Prior VIP usage and development experience is a plus

We are looking for experienced Senior/Lead ASIC Verification Engineers for our Noida-VIP team. Does this sound like a good role for you Experience : 5yrs to 15 years (multiple roles) Location: Noida Associated with Verification especially using industry-standard protocols & methodology Languages: Hands-on experience with System Verilog & Verilog . Should have a good understanding of Object Oriented Programming. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies . Protocol experience: Should have experience on any of the UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Please share your updated CV to [HIDDEN TEXT] or refer who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Show more Show less

At 7Rays Semiconductors, we specialize in providing comprehensive VLSI design solutions to assist our clients in achieving excellence in execution. Our team of experts is highly skilled in various areas including architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation. We utilize the latest technologies and methodologies to deliver top-notch solutions tailored to meet our clients" specific needs. As a Design Verification Engineer specialized in protocols such as PCIe, CXL, and UCIE, you will be responsible for: - Demonstrating expertise in interconnect protocols such as PCIe, CXL, and UCIE. - Having a solid understanding of AXI/ACE/CHI protocols, with a particular emphasis on AXI. - Knowledge of DMA usage and its applications. - Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). - Experience in utilizing standard Verification IP (VIP) in Testbenches, preferably Synopsys tools. - Familiarity with AI/ML network concepts is considered beneficial. - Additional proficiency in perl/tcl scripting would be advantageous. The ideal candidate for this role should possess a Bachelor's Degree in Electrical, Electronics, or Computer Engineering, along with 5-12 years of relevant experience. If you are passionate about semiconductor design, eager to work in a collaborative environment, and committed to delivering high-quality solutions, we would love to hear from you.,

You will be joining Insemi Technologies as a Staff or Lead Verification Engineer in Bengaluru. Your primary responsibility will be to own the functional verification of RTL designs for PCIe / UCIe protocols. This will involve building and enhancing UVM testbench components such as scoreboard, driver, and monitor. You will also be debugging complex design/verification issues and collaborating with teams to ensure architecture compliance. Additionally, you will play a key role in improving verification methodology and processes. To excel in this role, you should have at least 5-10 years of verification experience with a strong knowledge of PCIe and/or UCIe protocols. Expertise in SystemVerilog & UVM is essential, along with solid debugging and analytical skills. A degree in B.E/B.Tech or M.E/M.Tech in EE/CE or related fields is required, and any experience in VLSI design services would be a bonus. If you are passionate about PCIe / UCIe protocol verification and possess the necessary skills and experience, we encourage you to send your resume to Jennifer Margaret at jennifer.margaret@insemitech.com. Join us at Insemi Technologies and let's build something exceptional together.,

The DCAI and Silicon Eng Team is responsible for delivering leadership Xeon products to cloud and datacenter customers by developing industry-leading x86 core and differentiated IPs. These IPs enhance product performance and competitiveness in both Xeon and AI platforms. The IP design group within DCAI focuses on designing Coherent Fabric IP, Memory controller, NOC, PCIE, and other fundamental building blocks for Xeon server SOCs. We are currently looking for an experienced Senior Micro Architect to design, develop, and implement advanced Digital IO Controllers such as PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will possess a deep understanding of high-speed IOs like PCIe/CXL/UCIe architecture, interconnect protocols, and coherence mechanisms, along with a proven ability to implement these designs at the RTL level. Key Responsibilities: - Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs. - Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks. - Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs. - Collaborate closely with verification teams to create test plans and debug issues during pre-silicon validation. - Work with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems. - Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases. - Mentor junior engineers, contribute to technical reviews, and design documentation. - Stay updated with emerging technologies and trends in PCIe/CXL/UCIe protocols, as well as AI/ML hardware. - Demonstrate strong problem-solving and debugging skills. - Exhibit excellent communication and collaboration abilities. - Ability to manage and prioritize multiple tasks effectively. Qualifications: - Bachelor's degree with 15+ years of experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years. This is an Experienced Hire job type located in India, Bangalore, within the Design Engineering Group (DEG) at Intel. DEG is committed to developing best-in-class SOCs, Cores, and IPs that power Intel's products. The team focuses on delivering leadership products through the pursuit of Moore's Law and groundbreaking innovations. This role is eligible for a hybrid work model allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details, such as work model, location, or time type, are subject to change.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What Youll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What Youll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

Eridu AI India Private Limited, a subsidiary of Eridu Corporation, Saratoga, California, USA, invites highly motivated professionals to join its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup dedicated to enhancing training and inference performance for large AI models. By introducing innovative solutions in semiconductors, software, and systems, Eridu AI aims to optimize AI data center performance, increase GPU utilization, and reduce capex and power consumption. The company, backed by a team of experienced Silicon Valley executives and engineers, offers a unique opportunity to work on cutting-edge technology in the AI networking industry. As a Senior Manager at Eridu AI, you will lead the IC Verification team in Bengaluru, shaping the future of AI Networking. This role requires a self-driven individual with a passion for solving real-world problems and a desire to drive innovation in AI networking. Responsibilities: - Manage and lead the Bengaluru team of ASIC verification engineers, ensuring a collaborative work environment and effective communication across different locations. - Provide technical expertise in ASIC verification, ensuring compliance with industry standards and project specifications. - Conduct gate-level simulations, including timing and power analysis, to validate ASIC designs before tape-out. - Oversee RTL coverage analysis and provide feedback to enhance test suite thoroughness. - Collaborate with Firmware teams to ensure seamless integration between hardware and firmware components. - Mentor team members, identify training needs, and manage team augmentation in different locations. Qualifications: - ME/BE in Electrical Engineering, Computer Engineering, or related field. - Minimum 12 years of experience in ASIC verification, particularly in networking ASIC design. - Expertise in Hardware Verification Methodology, System Verilog, UVM, gate/timing/power simulations, and test-plan documentation. - Prior experience with Ethernet, UCIe, and PCIe protocols, high-speed SerDes, and global team management. - Excellent communication skills to lead and coordinate a diverse team effectively. Join Eridu AI to be part of a team that is revolutionizing AI infrastructure and shaping the future of AI networking. Your work will directly impact the next generation of AI networking solutions, pushing the boundaries of AI performance. The starting base salary will be determined based on skills, experience, qualifications, market trends, and comparable roles in the industry. Visit eridu.ai to learn more about our company and team.,

As a Design Verification Engineer at our company, you will be responsible for verifying high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field along with at least 4 years of hands-on experience in design verification. Your role will require expertise in SystemVerilog and UVM (Universal Verification Methodology) as well as a strong understanding of digital design principles, verification methodologies, and simulation tools. It is essential for you to be familiar with protocol specifications and industry standards for the interfaces mentioned above. You should have experience working with simulation tools like VCS, ModelSim, or Questa, and be proficient in debugging tools such as Waveform Viewers, Logic Analyzers, and protocol analyzers. The ability to write efficient and reusable verification components like scoreboards, monitors, and sequencers is crucial for this role. Strong problem-solving skills, attention to detail, and excellent communication skills are also required. You should be comfortable working in a collaborative environment and have a willingness to engage with team members effectively. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, proficiency in scripting languages for automation (e.g., Python), and familiarity with FPGA-based verification platforms and hardware debugging tools. If you are someone who enjoys working on challenging projects, has a passion for design verification, and meets the qualifications mentioned above, we would love to have you join our team in Bangalore or Hyderabad.,

Verification Engineer Location: Bengaluru Experience: 3+ Years Employment Type: Full-time Job Responsibilities: Create and carry out detailed plans to verify SoC systems. Design and manage test benches using SystemVerilog and UVM. Test the functionality, performance, and low-power aspects of designs. Identify and fix any design or verification problems on your own. Work with high-speed communication protocols like AXI, PCIe, Ethernet, CXL, and UCIe. Make sure that the design is thoroughly tested and follows the specifications. Skills Required: At least 3 years of experience in verifying SoC systems. Strong knowledge of SystemVerilog, UVM, and scripting languages like Python or Perl. Experience with simulation tools like VCS, Cadence, or Synopsys. Good understanding of communication protocols like AXI, PCIe, and Ethernet. Good problem-solving and analytical skills. Preferred Skills: Experience with UCIe (Universal Chiplet Interconnect Express) protocol is a plus. Interested candidates can share their resume to priya@maxvytech.com

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

Role & responsibilities Please interested candidate send me cv : galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name SoC NoC Verification Engineer Job No : PROX-14080 Position type: Permanent Total Exp: 7+ years to 15y HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: SoC NoC Verification Engineer with 7+ years of experience This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain test benches using SystemVerilog/UVM. Perform functional, performance, and power verification. Debug and resolve design and verification issues. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications. Client is looking for Network on chip , just look for the NoC verification AMD (Dont Share AMD Profiles) Preferred candidate profile

Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: SoC Network on Chip Verification Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: This role involves developing test plans, writing verification code, debugging issues, and collaborating closely with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures (for senior role). Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols: AXI, CHI, PCIe, Ethernet, CXL, UCIe. Manage testbench architecture and automation frameworks. Note : profiles with solid experience in SoC + NoC verification and exposure to the above protocols. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Sr Staff Engineer Design Verification [ Location: NOIDA] Job Description We are seeking a diligent Verification leader to join our team at leading semiconductor company. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers andmicroprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.

Develop emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers Write and maintain software components using C/C++ for emulation frameworks Create synthesizable RTL using Verilog for emulation model development Verify emulation models to ensure high performance, functionality, and reliability Collaborate with customers during deployment and debugging phases to ensure successful adoption Work with cross-functional teams to integrate emulation solutions across Synopsys products Maintain and update existing emulation platforms to comply with industry changes and customer needs The Impact You Will Have: Advance the development of standards-compliant and scalable emulation solutions Improve the performance and efficiency of semiconductor products through high-quality emulation Deliver superior customer support, enhancing the deployment experience and satisfaction Help Synopsys maintain a leadership position in silicon design and verification ecosystems Enable faster time-to-market for cutting-edge chips by providing robust emulation infrastructure Contribute to the adoption of next-gen interfaces and system-level design methodologies What You'll Need: 5+ years of relevant experience in semiconductor or hardware design domains Deep knowledge of PCIe, CXL, and UCIe protocol standards and usage Proficiency in C/C++ with strong object-oriented design understanding Good grasp of digital design concepts and proficiency in Verilog/SystemVerilog Experience with scripting languages such as Python, Perl, or TCL Familiarity with ARM architecture and functional verification (UVM) is a plus

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

• Working experience in IP/ASIC/ SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Role & responsibilities Preferred candidate profile