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Sr Principal RTL Design Engineer

12 - 20 years

4 - 10 Lacs

Posted:2 weeks ago| Platform: Foundit logo

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Work Mode

On-site

Job Type

Full Time

Job Description

12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.

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