Sr Principal RTL Design Engineer Cadence Design Systems

12.0 - 16.0 years

0 Lacs

karnataka

On-site

As an ASIC Design Engineer at Cadence, you will be responsible for: - Having 12+ years of experience in ASIC design - Being proficient in Verilog coding, RTL design, and complex control path and data path designs - Having knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA - Knowing RTL checks like LINT, SDC, CDC, synthesis flow, LEC, and timing constraints - Experience in writing Verilog testbench and running simulations You will be part of a team that is working on impactful technology solutions, pushing boundaries, and solving challenges that others cannot.,

Posted 1 week ago

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Sr Principal RTL Design Engineer Cadence Design Systems

12.0 - 16.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges tha...

Posted 2 months ago

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IP Logic Design Engineer Intel

6.0 - 10.0 years

0 Lacs

karnataka

On-site

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified...

Posted 3 months ago

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ASIC Digital Design Engineer, Senior Synopsys

2.0 - 7.0 years

2 - 7 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues cr...

Posted 5 months ago

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Staff ASIC RTL Digital Design Engineer Synopsys

5.0 - 10.0 years

5 - 8 Lacs

Pune, Maharashtra, India

On-site

Specifications Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts Exposure to quality processes in the context of IP design and verification is an added advantage Ability to work/ Prior experience as a Technical Lead for a small team is a major plus Should be able to ...

Posted 5 months ago

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