As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop. Key Responsibilities: - Execute block level floor planning, PG planning, partitioning, and placement - Perform tasks such as scan-chain reordering, clock tree synthesis, and timing optimization - Handle SI aware routing, timing analysis/closure, and ECO tasks - Conduct design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks - Implement physical design on advanced technology nodes like 28nm and 20nm - Demonstrate expertise in GDS To Netlift tool - Work with Semiconductors, Application Specific Integrated Circuit (ASIC), Synopsys, Floor Planning, GDS, and NETlift Qualifications Required: - Background in semiconductor/ASIC industry - Proficiency in GDS To Netlift tool - Familiarity with physical design implementation on advanced technology nodes - Knowledge of low power concepts and top-level physical design principles,

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Physical Design Lead