3.0 - 13.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced physical design engineer with a B. Tech / M. Tech (ECE) background and 3 to 13 years of experience, you will be responsible for a variety of tasks including top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs). Your expertise in SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, as well as experience in working on 65nm or lower node designs with advanced low power techniques, will be crucial for success in this role. Key Responsibilities: - Provide technical guidance and mentoring to phy...

Posted 1 day ago

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Electronic Design Automation Engineer Agivant Technologies

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced chip design engineer, you will be responsible for the following key domains: - Power Optimization: Utilize low-power design techniques and methodologies, including expertise in the Unified Power Format (UPF). - Timing Optimization: Demonstrate proficiency in static timing analysis (STA) and implement design constraints using the Synopsys Design Constraints (SDC) format. - Functional Safety Analysis: Apply a deep understanding of functional safety concepts and standards (e.g., ISO 26262), employing analysis techniques such as FMEDA and FTA. - Utilize industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys, Cadence, or Siemens EDA. - Proficiency ...

Posted 3 days ago

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Physical Design Lead CRB Tech Solutions Pvt. Ltd

5.0 - 9.0 years

0 Lacs

delhi

On-site

As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop....

Posted 2 weeks ago

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SOC DFT Lead/Manager Intel

8.0 - 15.0 years

0 Lacs

karnataka

On-site

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Posted 2 weeks ago

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ASIC Design Engineer Axiado

8.0 - 12.0 years

0 Lacs

hyderabad, telangana

On-site

Axiado is an AI-enhanced security processor company that is revolutionizing the control and management of digital systems. Founded in 2017, Axiado currently has a team of over 100 employees who are dedicated to developing cutting-edge technology. At Axiado, we believe that exceptional results are achieved through collaboration, respect, and going the extra mile. If you are passionate about disrupting the status quo, driving innovation, and making a difference in the world, we encourage you to apply for the following position. The ASIC/SoC Design position at Axiado offers you the opportunity to be part of a leading company in Smart Edge SoCs for network/systems control, management security sy...

Posted 1 month ago

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