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5.0 - 9.0 years

0 Lacs

delhi

On-site

As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop....

Posted 1 day ago

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