9 28Nm Jobs

Role Overview: You will be responsible for executing internal projects or small tasks of customer projects in the VLSI Frontend, Backend, or Analog design field with minimal supervision from the Lead. Key Responsibilities: - Work as an Individual contributor on tasks such as RTL Design, Module Verification, Physical Design, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. - Analyze and complete assigned tasks within defined domains successfully and on-time with minimal support from senior engineers - Ensure quality delivery approved by senior engineers or project lead - Verify quality using relevant metrics by Lead/Manager - Ensure timely delivery as per proje...

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 3+ Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16ff ...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop....

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to...

Along with GF- 28nm tech node is "Experience in Mixed signal and Digital hierarchical SoC Designs. Engineers with complete PnR knowledge, Signoff, timing and PV Experience in Mixed signal and Digital hierarchical SoC Designs.

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 8 10 Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16f...

Physical Design Engineer and Physican Design Lead positions for 3-5 years, 5-8 Years and 8-15 years of experience levels with hands on experience on technology nodes of 14nm, 28nm, 90nm, 180nm Must have Experience in Floorplanning, Power Grid Design, Placement, CTS, Routing, STA , Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology nodes of 14nm, 28nm, 90nm, 180nm Should have experience in Analog and Mixed Signal Design Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite Strong experience on Static Timing...