37 Ir Drop Jobs

As a Physical Design Engineer at Kinara, your role involves the following responsibilities: - Physical Design of complex data path and control blocks - Developing new techniques and flows to rapidly prototype hardware blocks - Developing flows that allow for detailed power estimation - Working with the design team to understand placement and recommend implementation options - Interacting and engaging with external teams to drive as well as deliver subsystems leading to chip tapeout Preferred qualifications for this position include: - BTech/MTech EE/CS with 8+ Years of Physical Design experience - Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout tec...

Work on Low-power implementation and/or EMIR(electro-migration/IR-drop) analysis of state-of-the-art SOCs at cutting edge FinFET technology nodes for various customers. This position is for a senior-level physical design engineer who will work on Low-power implementation of of a complex SOC/block-level based on UPF/CPF EMIR analysis of complex SOC/Block-level Static/Dynamic analysis, power calculation Work hands-on to solve critical design and execution issues related to low-power, EMIR Own power-domain implementation flows, sign-off methodologies for execution of SoCs Interested can send updated resumes to basheer.unnisa@leadsoc.com

Hiring: Senior Analog Layout Design Leads & Architects Location: Bengaluru/Visakhapatnam Experience: 10+ Years Company: Eximietas Design...! Greetings from Eximietas Design! We are looking for an experienced Senior Analog Layout Design Leads & Architects to join our team in the Bengaluru/Visakhapatnam Location. Required Technical Expertise: We're looking for highly skilled professionals with strong expertise in lower FINFET technology nodes to contribute to cutting-edge analog layout development. Key Skills & Requirements: Deep knowledge of IR drop , Electromigration , self-heating , RC delay , and parasitic capacitance optimization Strong understanding of layout impact on circuit performanc...

As a Digital/Memory Mask Design Engineer at NVIDIA, you will be part of a dynamic team responsible for handling challenging high-speed digital memory circuit designs. NVIDIA, a company that constantly evolves and strives to amplify human creativity and intelligence, is looking for individuals excited to make a lasting impact on the world. **Role Overview:** You will be responsible for implementing IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes, leading the architecture and layout design of key memory subsystems, and optimizing all physical verification activities. Your role will involve driving the identification and resolution of...

As a Senior Analog Layout Design Lead or Architect at Eximietas Design, you will have the opportunity to contribute to cutting-edge analog layout development using advanced lower FINFET technology nodes. Your role will involve deep knowledge of IR drop, Electromigration, Self-heating, RC delay, and Parasitic capacitance optimization. You will be responsible for understanding the layout impact on circuit performance, delivering high-quality layouts under tight design constraints, and utilizing Cadence/Synopsys layout tools and flows. Familiarity with PERL / SKILL scripting would be an added advantage. Strong communication skills and experience collaborating with cross-functional engineering t...

Position: Sr Design Lead (PNR)/STA Experience: 8-12 years relevant experience. Location Bangalore/Hyderabad Tessolve Semiconductors a venture of Hero Electronix , part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even ...

Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the worlds most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon ...

Notice Period : 0 - 30 Days Mode : Onsite work Role Description This is a full-time on-site role in Bengaluru, for a Physical Design Engineer having 3 - 10 years of experience. The Physical Design Engineer will be responsible for designing, implementing, and verifying low power high-performance integrated circuits on both advanced technologies and established technology nodes. The Physical Design Engineer will also work closely with cross-functional teams to identify and solve physical design-related issues, driving feasibility and optimization of design and implementation flows. Qualifications Minimum 3 years of relevant experience as a Physical Design Engineer Experience in designing with ...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be part of a rapidly growing team specializing in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Solid understanding of how layout impacts circuit performance, such as speed and area - Ability to implement layouts that meet strict design constraints while ensuring high quality - Proficiency in CADENCE/SYNOPSYS layout tools and flows - Familiarity with scripting languages like PERL/SKILL would be advantageous - Strong communicat...

Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physic...

Job Overview We are seeking a talented Analog Layout Engineer with 3- 5 years of experience in advanced semiconductor technologies (5nm and below). The ideal candidate will have hands-on expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre. This is a fantastic opportunity to work on cutting-edge analog and mixed-signal circuit layouts as part of a high-performance team. Key Responsibilities Execute full custom layout design for high-speed analog and mixed-signal blocks. Collaborate closely with circuit design teams to interpret and implement layout specifications. Perform layout verification, including DRC, LVS, and parasitic extraction ...

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

Role Overview: As an Analog Layout Engineer at Eximietas, you will be responsible for critical analog layout design of various blocks such as LDOs, DC-DC converters, ADC/DACs, PLLs, Oscillators, Temperature sensors, Bandgap references, voltage monitors, Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE. Key Responsibilities: - Hands-on experience in critical analog layout design - Understanding and managing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Knowledge of layout effects on circuit performance such as speed and area - Implementing high-quality layouts based on design constraints - Collaboration with cross-functional teams - P...

As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop....

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture. Experience with constraints, synthesis or Clock Tree Synthesis (CTS)...

As a Physical Design Engineer at Kinara, you will play a crucial role in the development of complex data path and control blocks. Your responsibilities will include: - Developing new techniques and flows to rapidly prototype hardware blocks. - Implementing flows that allow for detailed power estimation. - Collaborating with the design team to understand placement and recommend implementation options. - Engaging with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include: - BTech/MTech EE/CS with 8+ years of Physical Design experience. - Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout t...

Role Overview: As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: - Define architecture and design specifications for custom memory IPs. - Optimize circuits such as memory cell arrays, sense amplifiers, and decoders. - Lead schematic-level design and simulation. - Collaborate with layout and verification teams. - Guide post-layout activi...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross...

As a Senior Analog Layout Design Engineer / Lead at Eximietas Design, your role will involve optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You are expected to have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. Your responsibilities include understanding how layout impacts circuit performance, implementing high-quality layouts meeting tight design constraints, and collaborating with cross-functional teams. Key Responsibilities: - Optimize IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. - Understand and mitigate the im...

Role Overview: As a member of ST, you will be contributing to the design Implementation (RTL2GDSII) of products related to Engine control, Safety (including airbag), Body, Chassis, and Advanced Driver Assistance System (ADAS) for futuristic cars. You will be responsible for guiding and reviewing the work done by younger engineers, as well as being a strong technical contributor. This role requires strong communication and interpersonal skills for synthesizing and reporting data to management and customers. You will be working on Chip and IP Implementation using cutting-edge technologies like 7nm FINFET and 28FDSOI, from RTL to GDSII. Constantly challenged to meet automotive standards while c...

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic ...

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability t...

As a Senior/Lead Engineer in Bengaluru, India, you will need a minimum of 35/57 years of industry experience, respectively. Your educational background should include a B.E./B.Tech in Electronics, Electrical, Electronics & Communication, or related field, while a preferred qualification would be an M.E./M.Tech in VLSI Design, Microelectronics, or a related specialization. Candidates from semiconductor service or product companies are welcome, with a strong emphasis on hands-on expertise in Physical Design and EDA tool flows. Your responsibilities will revolve around owning the end-to-end Physical Design flow, including floorplanning, placement, CTS, routing, ECOs, IR drop analysis, and physi...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...