30 Ir Drop Jobs

Notice Period : 0 - 30 Days Mode : Onsite work Role Description This is a full-time on-site role in Bengaluru, for a Physical Design Engineer having 3 - 10 years of experience. The Physical Design Engineer will be responsible for designing, implementing, and verifying low power high-performance integrated circuits on both advanced technologies and established technology nodes. The Physical Design Engineer will also work closely with cross-functional teams to identify and solve physical design-related issues, driving feasibility and optimization of design and implementation flows. Qualifications Minimum 3 years of relevant experience as a Physical Design Engineer Experience in designing with ...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be part of a rapidly growing team specializing in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Solid understanding of how layout impacts circuit performance, such as speed and area - Ability to implement layouts that meet strict design constraints while ensuring high quality - Proficiency in CADENCE/SYNOPSYS layout tools and flows - Familiarity with scripting languages like PERL/SKILL would be advantageous - Strong communicat...

Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physic...

Job Overview We are seeking a talented Analog Layout Engineer with 3- 5 years of experience in advanced semiconductor technologies (5nm and below). The ideal candidate will have hands-on expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre. This is a fantastic opportunity to work on cutting-edge analog and mixed-signal circuit layouts as part of a high-performance team. Key Responsibilities Execute full custom layout design for high-speed analog and mixed-signal blocks. Collaborate closely with circuit design teams to interpret and implement layout specifications. Perform layout verification, including DRC, LVS, and parasitic extraction ...

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

Hiring Senior VLSI Engineer (10+ yrs) with strong experience in Low-Power Implementation, EMIR Analysis (Static/Dynamic), and SoC Physical Design using Redhawk/Voltus, ICC2/Innovus. Required Candidate profile Experienced SoC PD engineer skilled in EMIR, low-power design, PnR, STA, DRC/LVS, and sign-off. Strong in TCL/Perl scripting, tool automation, and FinFET node implementation.

Role Overview: As an Analog Layout Engineer at Eximietas, you will be responsible for critical analog layout design of various blocks such as LDOs, DC-DC converters, ADC/DACs, PLLs, Oscillators, Temperature sensors, Bandgap references, voltage monitors, Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE. Key Responsibilities: - Hands-on experience in critical analog layout design - Understanding and managing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization - Knowledge of layout effects on circuit performance such as speed and area - Implementing high-quality layouts based on design constraints - Collaboration with cross-functional teams - P...

As a Physical Design Implementation Engineer in the semiconductor/ASIC industry, your role will involve various tasks on advanced technology nodes such as 28nm and 20nm. You will be responsible for block level floor planning, PG planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks encompassing both timing and functional ECOs. Additionally, you will handle SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks. It is crucial to possess a solid understanding of low power concepts, top-level physical design, partitioning, timing constraints, and IR Drop....

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with computer architecture. Experience with constraints, synthesis or Clock Tree Synthesis (CTS)...

As a Physical Design Engineer at Kinara, you will play a crucial role in the development of complex data path and control blocks. Your responsibilities will include: - Developing new techniques and flows to rapidly prototype hardware blocks. - Implementing flows that allow for detailed power estimation. - Collaborating with the design team to understand placement and recommend implementation options. - Engaging with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include: - BTech/MTech EE/CS with 8+ years of Physical Design experience. - Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout t...

Role Overview: As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: - Define architecture and design specifications for custom memory IPs. - Optimize circuits such as memory cell arrays, sense amplifiers, and decoders. - Lead schematic-level design and simulation. - Collaborate with layout and verification teams. - Guide post-layout activi...

As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross...

As a Senior Analog Layout Design Engineer / Lead at Eximietas Design, your role will involve optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You are expected to have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. Your responsibilities include understanding how layout impacts circuit performance, implementing high-quality layouts meeting tight design constraints, and collaborating with cross-functional teams. Key Responsibilities: - Optimize IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. - Understand and mitigate the im...

Role Overview: As a member of ST, you will be contributing to the design Implementation (RTL2GDSII) of products related to Engine control, Safety (including airbag), Body, Chassis, and Advanced Driver Assistance System (ADAS) for futuristic cars. You will be responsible for guiding and reviewing the work done by younger engineers, as well as being a strong technical contributor. This role requires strong communication and interpersonal skills for synthesizing and reporting data to management and customers. You will be working on Chip and IP Implementation using cutting-edge technologies like 7nm FINFET and 28FDSOI, from RTL to GDSII. Constantly challenged to meet automotive standards while c...

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic ...

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability t...

As a Senior/Lead Engineer in Bengaluru, India, you will need a minimum of 35/57 years of industry experience, respectively. Your educational background should include a B.E./B.Tech in Electronics, Electrical, Electronics & Communication, or related field, while a preferred qualification would be an M.E./M.Tech in VLSI Design, Microelectronics, or a related specialization. Candidates from semiconductor service or product companies are welcome, with a strong emphasis on hands-on expertise in Physical Design and EDA tool flows. Your responsibilities will revolve around owning the end-to-end Physical Design flow, including floorplanning, placement, CTS, routing, ECOs, IR drop analysis, and physi...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design cons...

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Re...

You will be part of Kinara, a Bay Area-based venture backed company, founded based on research conducted at Stanford University. Kinara's game-changing AI solutions aim to revolutionize what individuals and businesses can accomplish. Their Ara inference processors, combined with an innovative SDK, offer unparalleled deep learning performance at the edge. This enables the acceleration and optimization of real-time decision-making, emphasizing the importance of speed and power efficiency. By embedding high-performance AI into edge devices, Kinara contributes to creating a smarter, safer, and more enjoyable world. As the field of Edge AI is on the verge of a significant growth phase, Kinara is ...

We are seeking a Digital/Memory Mask Design Engineer who is enthusiastic about joining a dynamic team of individuals tasked with managing complex high-speed digital memory circuit designs. At NVIDIA, we have a history of reinventing ourselves. Our creation of the GPU has driven the growth of the PC gaming industry, redefined modern computer graphics, and transformed parallel computing. Today, the field of artificial intelligence is rapidly expanding globally, necessitating highly scalable and massively parallel computational power in which NVIDIA GPUs excel. NVIDIA is a constantly evolving entity that thrives on seizing new opportunities that are uniquely challenging, can only be tackled by ...

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout act...

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts th...

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area...