9 Ir Drop Jobs

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL is a plus. Strong communication skills are necessary as you will be working with cross-functional teams. If you are interested in this opportunity or know someone who would be suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Requirements: - Proficiency in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Strong comprehension of how layout impacts circuit performance metrics such as speed and area. - Ability to create layouts that meet rigorous design constraints and uphold quality standards. - Hands-on experience with CADENCE/SYNOPSYS layout tools and workflows. - Familiarity with scripting languages such as PERL/SKILL is considered a plus. - Excellent communication skills with a proven track record of collaborating effectively with cross-functional teams. If this opportunity aligns with your expertise and interests, or if you know someone who would be a suitable fit, please forward your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Best regards, Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Email: maruthiprasad.e@eximietas.design Phone: +91 8088969910,

You will be part of Kinara, a Bay Area-based venture backed company, founded based on research conducted at Stanford University. Kinara's game-changing AI solutions aim to revolutionize what individuals and businesses can accomplish. Their Ara inference processors, combined with an innovative SDK, offer unparalleled deep learning performance at the edge. This enables the acceleration and optimization of real-time decision-making, emphasizing the importance of speed and power efficiency. By embedding high-performance AI into edge devices, Kinara contributes to creating a smarter, safer, and more enjoyable world. As the field of Edge AI is on the verge of a significant growth phase, Kinara is poised to play a pivotal role in this evolution. Your responsibilities will include the physical design of complex data path and control blocks, development of new techniques and flows for rapid hardware prototyping, creation of flows enabling detailed power estimation, collaboration with the design team to understand placement and recommend implementation options, as well as engagement with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include a BTech/MTech degree in EE/CS with at least 8 years of experience in Physical Design. You should possess extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout techniques, along with skills in Physical verification and quality checks such as LVS, DRC, IR drop, Clock tree synthesis, Power mesh design, and Signal integrity. Familiarity with the latest foundry nodes up to 7nm is desirable, as well as hands-on experience with various design aspects including Synthesis, Place-and-route, Full Chip STA, IO Planning, Floorplan, Power Mesh creation, Bump Planning, RDL Routing, and Low power design flows. Strong expertise in advanced digital design architectures and clocking structures is essential to manage timing and physical design constraints effectively. Furthermore, you should be able to collaborate with designers to analyze and explore physical implementation options for complex designs, possess basic knowledge of DFT techniques, and be familiar with industry-standard PnR, Synthesis, and TCL Scripting tools. Strong communication skills and the ability to work well in a team are also crucial. At Kinara, the work culture is centered around fostering innovation. The environment encourages professionals to tackle exciting challenges under the guidance of technology experts and mentors. The company values diverse perspectives and shared responsibilities, creating a collaborative and inclusive atmosphere where every individual's input is respected and appreciated. If you are passionate about making an impact and are eager to take on rewarding challenges, Kinara awaits your application eagerly. Join Kinara and be a part of a dynamic team that values innovation, collaboration, and personal growth. Your unique skills and experiences will contribute to shaping the future of AI solutions and advancing the field of Edge AI. Share your story with us, and let's work together to create a smarter, safer, and more enjoyable world.,

We are seeking a Digital/Memory Mask Design Engineer who is enthusiastic about joining a dynamic team of individuals tasked with managing complex high-speed digital memory circuit designs. At NVIDIA, we have a history of reinventing ourselves. Our creation of the GPU has driven the growth of the PC gaming industry, redefined modern computer graphics, and transformed parallel computing. Today, the field of artificial intelligence is rapidly expanding globally, necessitating highly scalable and massively parallel computational power in which NVIDIA GPUs excel. NVIDIA is a constantly evolving entity that thrives on seizing new opportunities that are uniquely challenging, can only be tackled by us, and hold significance for the world. Our mission is to enhance human creativity and intelligence. As a member of the NVIDIA team, you will be immersed in a diverse and supportive environment where everyone is encouraged to deliver their best work. Join our diverse team and discover how you can leave a lasting impact on the world! Your responsibilities will include: - Executing IC layout for innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, and lower nodes using industry-standard methodologies. - Leading the architecture and layout design of critical memory subsystems, such as control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. - Overseeing custom layout and verification of complex memory cells, establishing standards and methodologies for compiler-driven design flows. - Managing and optimizing all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. - Identifying and resolving intricate physical design issues in compiler-generated layouts, while mentoring junior engineers in established methodologies. - Providing expertise on IR drop and EM mitigation strategies, creating design methodologies for resilient memory layouts. - Demonstrating deep knowledge in ultra-deep sub-micron layout challenges, regularly introducing and implementing advanced solutions. - Developing memory compilers, leading problem-solving efforts, and driving optimization for performance, area, and manufacturability. - Fostering effective teamwork across cross-functional teams, influencing project direction and ensuring alignment with organizational goals. - Excelling in resource management, representing the team in technical discussions with customers. - The layout of IP will feature significant digital components. - Embracing and implementing the best layout practices/methodology for composing digital Memory layouts. - Adhering to company procedures and practices for IC layout activities. Desired qualifications: - B.E/B Tech. / M Tech in Electronics or equivalent experience with a minimum of 2 years" proven expertise in Memory layout in advanced CMOS processes. - Proficiency in industry-standard EDA tools for Cadence. - Experience in laying out high-performance memories of various types. - Knowledge of Layout fundamentals, including different bit cells, Decoders, LIO, etc. (matching devices, symmetrical layout, signal shielding). - Experience with floor planning, block-level routing, and macro-level assembly. - Profound understanding of top-level verification, including EM/IR quality checks, and detailed knowledge of layout-dependent effects such as LOD, Dummification, fills, etc. #LI-Hybrid,

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts that meet tight design constraints. Key Skills & Requirements: - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Solid understanding of how layout impacts circuit performance. - Ability to implement layouts meeting tight design constraints and delivering high quality. - Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. - Familiarity with scripting languages (PERL/SKILL) is a plus. - Strong communication skills and experience collaborating with cross-functional teams. If you find this opportunity intriguing or know someone who would be a good fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Contact: +91 8088969910.,

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross-functional teams are also key to success in this role. If you are interested in this opportunity or know someone suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are looking forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design. Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Role & responsibilities JD: Advanced memory layout design (SRAM, ROM, custom) Hands-on with FinFET, Virtuoso, Calibre, PVS Tight collaboration with circuit & verification teams Mastery in DRC/LVS, parasitic optimization, and layout efficiency Experience with foundry tech files and tapeout is a huge plus!

You are invited to join Eximietas Design as a Senior Analog Layout Design Engineer/Lead with 7-15 years of experience. We are a rapidly growing team seeking professionals skilled in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. Your key responsibilities will include expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You must be able to implement layouts that meet strict design constraints while ensuring high quality. Proficiency in CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL would be advantageous. Strong communication skills are necessary as you will collaborate with cross-functional teams. If you are interested in this exciting opportunity or know someone who might be a suitable fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated, and we are eager to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to welcoming you to our dynamic team at Eximietas Design.,