27 Power Optimization Jobs

As a SoC Power Management Design Engineer at AMD, your role will involve developing and designing custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. You will collaborate with the lead SoC architect to define customer-specific architectures, contribute to product specifications, and make performance and power trade-offs. Your work will span from early concept development through final production, requiring excellent organization and communication skills. You will work with expert architects and designers globally, presenting your findings to colleagues and customer engineering teams. Key Responsibilities: - Drive physical design and power architecture based on customer-specific requirements - Collaborate with AMD's Engineering teams and IP teams to aid in integration, implementation, and optimization of designs - Analyze power consumption and delivery using static, dynamic models, and emulation data - Evaluate performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches, and network-on-chip fabric - Establish voltage-frequency design points in collaboration with technology teams, silicon validation, and product engineering teams - Define definitions for on-die PDN, power gating, package, and system power delivery in coordination with systems and architecture team - Analyze effects of control algorithms for management throttling mechanisms to optimize performance within thermal and peak current limits Preferred Experience: - Solid understanding of SoC construction, including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging - Strong knowledge of SoC power management, power dissipation, and mobile battery life - Proficiency in scripting, data analysis, EDA tools, physical design tools for power optimization, VLSI design flow, and CMOS technology - Ability to model thermal control loops and throttling mechanisms - Strong problem-solving, organizational, and communication skills with the ability to work in a dynamic and diverse environment - Proficiency in scripting languages, particularly Python, is highly preferred - Experience with Power Architect, Power Artist, and VisualSim is a plus - Detail-oriented thinking skills and ability to tackle novel problems from different perspectives and levels of abstraction - Capability to analyze and streamline sophisticated workflows and processes through innovative automation Academic Credentials: - Bachelors or Masters degree in computer engineering/Electrical Engineering (Note: The benefits offered are described separately in the AMD benefits overview.),

Embedded Firmware Engineer with expertise in C/C++, CAN/ethernet, Cortex M4, debugging & protocol integration. Responsible for design, coding, testing & optimization of embedded systems. Required Candidate profile BE/BTech/ME/MTech in Electronics with 3–7 yrs exp in Embedded C/C++, CAN, Cortex M4, UART, SPI, I2C. Skilled in debugging,interrupt-based design,RTOS,Modbus & wireless tech Self-starter,problem-solver

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the semiconductor industry, you thrive in dynamic, fast-paced environments and have successfully led teams through multiple tapeoutsat least two of which you have completed independently. Your hands-on knowledge of physical design implementation, timing closure, power optimization, and physical verification using industry-standard tools sets you apart as a technical authority in your field. You bring a holistic understanding of the chip design flow, and your familiarity with both front-end and back-end design methodologies allows you to bridge gaps across the development cycle. Your leadership style is inclusive and motivating, fostering a culture of innovation, collaboration, and continuous learning within your team. You are adept at project and technical management, ensuring milestones are met while maintaining the highest standards of quality and efficiency. Your communication skills are exceptional, enabling you to interact effectively with cross-functional teams, foundry partners, and customers alike. You are driven by the excitement of building next-generation embedded memory products and thrive on solving complex engineering challenges. You value diversity, are committed to mentoring others, and believe in empowering your team to achieve their best. If you are ready to make a tangible impact on cutting-edge silicon validation and design, Synopsys offers the perfect environment for your ambitions. What Youll Be Doing: Leading and mentoring a high-performing team responsible for physical design implementation and tape out of advanced ASICs and test chips. Driving end-to-end chip design flow, from RTL to GDSII, ensuring successful execution of multiple projects. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Collaborating closely with front-end design, silicon validation, and software teams to deliver robust and efficient solutions. Managing project schedules, resource allocation, and risk mitigation to ensure timely and successful tape outs. Acting as the technical point of contact for foundry interactions and customer communications throughout the design and post-silicon support phases. Championing best practices in design methodology, quality assurance, and continuous process improvement. The Impact You Will Have: Delivering high-quality, high-performance test chips that enable next-generation embedded memory products. Accelerating time-to-market for Synopsys customers by ensuring robust and timely tape outs. Enhancing the companys technical reputation through successful project delivery and customer satisfaction. Driving innovation in physical design methodologies and tool flows to optimize efficiency and reliability. Mentoring and developing the next generation of engineering talent within the organization. Strengthening key partnerships with foundries and customers through proactive engagement and technical leadership. Contributing to the strategic direction of the Silicon Validation Design Team and influencing future product development. What Youll Need: 10-15 years of hands-on experience in ASIC physical design, with at least 5 years in a leadership role. Proven track record of multiple successful tape outs (minimum two completed independently). Expertise in physical design implementation, timing closure, power and physical verification using industry-standard EDA tools. Strong understanding of the complete chip design flow, from RTL to GDSII. Experience in project technical management, people management, and cross-functional collaboration. Knowledge of front-end design and RTL methodologies is a significant plus. Who You Are: Inspirational leader with a collaborative and inclusive approach to team management. Excellent communicator, able to articulate complex technical concepts to diverse audiences. Analytical thinker with strong problem-solving skills and a detail-oriented mindset. Adaptable, proactive, and comfortable making decisions in fast-paced, evolving environments. Committed to continuous learning, mentoring, and fostering a culture of growth and innovation. The Team Youll Be A Part Of: You will join the Silicon Validation Design Team, a passionate group dedicated to designing and developing test chips for embedded memory products. Our unique strength lies in owning the process end-to-endfrom RTL to GDSII tape out and post-silicon supportwhile engaging directly with foundry partners and customers. We pride ourselves on innovation, technical excellence, and a collaborative spirit that drives continuous improvement and customer success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

The ASIC Design Senior Engineer plays a critical role in the development and implementation of advanced integrated circuit designs within the organization. You will be instrumental in driving innovation and ensuring that the products maintain a competitive edge in the rapidly evolving semiconductor industry. Your responsibilities will include contributing technical expertise and leadership in the ASIC design process, from initial concept through to production. Working collaboratively with cross-functional teams, you will solve complex design challenges, optimize performance, and ensure adherence to industry standards. In addition to deep technical knowledge, this role will require the ability to mentor junior engineers and lead project initiatives. Your strong background in digital and analog design, along with a proven track record of delivering projects on time and within budget, will be essential in shaping the future of the technology solutions and impacting the company's success. Key Responsibilities: - Design and validate complex ASICs in accordance with specifications. - Develop RTL using Verilog/System Verilog for various digital components. - Conduct simulation and verification of designs using advanced methodologies. - Execute timing analysis and optimization to meet performance requirements. - Collaborate with cross-functional teams including hardware, software, and test engineering. - Perform power estimation and drive strategies for low-power design. - Oversee the transition from design to tape-out and ensure compliance with DFT standards. - Mentorship and training of junior engineers and interns in design practices. - Participate in design reviews and provide constructive feedback. - Address and resolve design-related issues throughout the lifecycle. - Communicate effectively with project managers to ensure timelines are met. - Document design processes and maintain accurate design records. - Utilize FPGA devices for prototyping and testing of ASIC functionalities. - Research and implement new design tools and methodologies. - Keep updated with industry trends and advancements in ASIC technology. Required Qualifications: - Bachelor's or Master's degree in Electrical Engineering or related field. - Minimum of 5 years of experience in ASIC design and development. - Strong experience with digital circuit design and verification methodologies. - Proficient in Verilog and System Verilog programming. - Hands-on experience with tools such as Cadence, Synopsys, and Mentor Graphics. - Familiarity with FPGA development and prototyping techniques. - Demonstrated experience in timing closure and power optimization. - Solid understanding of DFT concepts and techniques. - Ability to mentor junior engineers and lead design projects. - Excellent problem-solving and analytical skills. - Strong communication skills, both verbal and written. - Ability to work collaboratively in a fast-paced environment. - Knowledge of industry standards and best practices in ASIC design. - Experience with scripting languages such as Perl or Python is a plus. - Strong organizational skills and attention to detail. - Demonstrated track record of successful project delivery. Skills: system verilog, problem solving, simulation and verification, power optimization, DFT, timing analysis, schematic capture, FPGA development, low-power design, DFT standards, SoC, scripting languages (Perl, Python), Verilog, digital circuit design, RTL coding, ASIC design, power estimation.,

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. is a critical part of the role. Proficiency in Tcl/Perl Scripting is required. Experience in working as part of a larger team, meeting project milestones and deadlines, and handling technical deliverables with a small team of engineers is expected. Strong problem-solving skills and good communication skills are essential. Qualcomm India Private Limited is looking for candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience will be considered. A PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience are also acceptable. Qualcomm is an equal opportunity employer and is committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact Qualcomm at disability-accommodations@qualcomm.com. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and protection of Company confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm. Unsolicited submissions from agencies or individuals being represented by an agency will not be considered. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. The role involves Physical Implementation activities for high-performance Cores for various technologies, including floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure, power optimization, and more. The ideal candidate should have exposure to PD implementation of PPA critical cores, timing convergence of high-frequency data-path intensive Cores, advanced STA concepts, clocking architecture, and should be proficient in Tcl/Python/Perl Scripting for automation. Strong problem-solving skills, communication skills, and the ability to work well in a team are essential. Collaboration with design, DFT, and PNR teams to support issue resolutions is also a key aspect of the role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Recruitment agencies are advised that Qualcomm's Careers Site is intended for individuals seeking jobs at Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required for this role. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. Proficiency in Tcl/Perl Scripting and strong problem-solving skills, along with effective communication skills, are vital for this position. Qualcomm India Private Limited is seeking candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in a relevant field and 1+ year of Hardware Engineering experience, or a PhD in a related field, are also acceptable qualifications. The ideal candidate should have 1-3 years of experience in Physical Design/Implementation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to security and the protection of Company and proprietary information. It is essential to ensure workplace accessibility for individuals with disabilities. For further information about this role, please contact Qualcomm Careers.,

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexities. Your contribution will be crucial in driving continuous improvement in PPA and turnaround time (TAT) metrics. To excel in this role, you must possess deep knowledge of synthesis, timing closure, power optimization, and constraints management. Your experience with low-power, high-performance design at advanced nodes below 5nm will be valuable. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX is required to effectively carry out your responsibilities. Familiarity with scripting languages such as TCL, Perl, and Python will aid in performing tasks efficiently. A BS or MS in Electrical Engineering or a related field along with 9+ years of relevant experience is necessary to succeed in this position.,

The Android Automotive Lead role requires 5-10 years of experience in the relevant field and a BE, B.Tech / ME, M.Tech educational qualification. This position is based in Bangalore. As an Android Automotive Lead, you will need to demonstrate expertise in Android Dev, Android NDK, C/C++/Java, and Automotive Domain. Your responsibilities will include: - Proficiency in Android-Auto, AOSP Framework, Framework Optimization, IPCs, and android ecosystems. - Knowledge of Android, Linux, and QNX middleware/frameworks, MM HALs such as Audio, Video, Camera, Display, Graphics, and AI. - Development skills in Android, Linux, and QNX frameworks, as well as experience with Hypervisors, Virtual Machines (VMs), Virtual driver development, and Linux Containers. - Understanding of security features in QNX/Android systems like Verified Boot, se-linux, SMAC, IMA/EVM, etc. - Android-Native Development (NDK) and Java Native Interface (JNI) proficiency. - Programming expertise in C, C++, Java, and Multithreaded programming. - Experience in Boot, power, and performance optimizations, as well as knowledge of Automotive Safety concepts and security threat analyses to meet ISO26262, ISO21434, and ASPICE process requirements. - Familiarity with vehicle infotainment features and third-party app integration. This position falls under the job category of Digital Technologies.,

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Role Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area / power / performance / convergence) , develop plans and deploy/support them Power performance area improvement using synthesis and place and route tools. Support physical design flows using icc2/innovus tools Provide tool support and issue debugging services to physical design team engineers across various sites Develop and maintain 3rd party tool integration and productivity enhancement routines Understand advance tech PNR and STA concents and methodologies and work closely with EDA vendors to deploy solutions. Skill Set Good TCL, Perl programming skills Knowledge of one of Encounter/Innovus or Icc2 or Olympus tool (or other equivalent PNR tool) is mandatory Basic understanding of Timing/Formal verification/Physical verification/extraction are desired Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 15+ years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter / Innovus / edi / Icc2 / Olympus / Nitro (or other equivalent PNR tool). One or more of the above is mandatory* Technology enablement for sub-5nm nodes from primary process nodes.

You will be responsible for designing and optimizing memory architectures for high-performance and low-power applications as a skilled SRAM & ROM IC Memory Design Engineer. Your main tasks will include designing, simulating, and verifying SRAM and ROM memory blocks while collaborating with cross-functional teams in circuit design, layout, verification, and technology development. Key responsibilities for this role include designing and developing SRAM and ROM memory architectures for various semiconductor applications, performing transistor-level circuit design and simulation, optimizing power, performance, and area (PPA) of memory designs, conducting timing, reliability, and variation analysis, working closely with physical design engineers, implementing redundancy and error correction techniques, and supporting design verification and validation processes. To qualify for this position, you should have a Bachelor's or Master's degree in Electrical Engineering or a related field, along with at least 3 years of experience in SRAM/ROM memory design for semiconductor applications. Strong knowledge of CMOS circuit design, transistor-level simulation, and memory architecture is required, as well as experience with circuit simulators such as SPICE, Spectre, HSPICE, and proficiency in tools like Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. Join us at onsemi (Nasdaq: ON), where we are dedicated to driving disruptive innovations for a better future, focusing on automotive and industrial end-markets. We are at the forefront of megatrends such as vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a diverse and innovative product portfolio, we create intelligent power and sensing technologies that address the world's most complex challenges and pave the way towards a safer, cleaner, and smarter world. For more information on our company benefits, please visit: https://www.onsemi.com/careers/career-benefits At onsemi, we are committed to attracting high-performance innovators and providing all candidates with a positive recruitment experience that showcases us as a great place to work.,

As an experienced professional in the field of semiconductor design, you will be involved in working on advanced technology nodes such as 7nm/5nm or lower, collaborating closely with a diverse range of customers to deliver cutting-edge solutions. Your role will primarily revolve around addressing and resolving critical design issues to meet performance, area, and power requirements. One of your key responsibilities will be to develop innovative flows and methodologies for efficient placement, clock tree synthesis (CTS), and routing. Your expertise in these areas will be instrumental in ensuring the successful implementation of complex designs and meeting project goals effectively. Additionally, you will play a crucial role in providing comprehensive training and technical support to our valued customers. By sharing your knowledge and insights, you will help them optimize their design processes and achieve superior results. Overall, this role offers a dynamic and challenging environment where your skills and expertise will contribute significantly to the success of our projects and the satisfaction of our clients.,

As an R&D Engineer at Synopsys, you play a crucial role in driving innovation in the field of physical design, with a focus on high-performance cores and IPs. Your deep understanding of physical design, coupled with your expertise in place & route, timing closure, and power optimization, enables you to tackle complex design challenges with ease. Your proficiency in low-power, high-performance design, particularly with advanced nodes under 5nm, sets you apart in the industry. Your responsibilities include developing and implementing innovative methodologies for high-performance cores and IPs, collaborating with a global team to enhance Performance, Power, and Area (PPA) metrics, and utilizing advanced technologies and tools to improve design quality and process efficiency. You will contribute to both flow development and the implementation of complex IPs, addressing critical design challenges using Synopsys implementation tools. Your impact as an R&D Engineer at Synopsys is significant, as you drive innovation in high-performance core and IP implementation methodologies, enhance the efficiency and predictability of the implementation process, and contribute to the development of cutting-edge semiconductor technologies. By solving complex design challenges and supporting the continuous advancement of Synopsys" technological capabilities, you play a key role in achieving best-in-class PPA and TAT targets. To excel in this role, you must possess deep knowledge of physical design, place & route, timing closure, and power optimization, along with experience in low-power, high-performance design and advanced nodes under 5nm. Proficiency in industry-leading tools like Fusion Compiler, Primetime, and Formality, as well as scripting languages such as TCL, Perl, and Python, is essential. A BS or MS in Electrical Engineering or a related field with 5+ years of relevant experience is required. Additionally, your self-motivation, strong investigative and problem-solving skills, enthusiasm for learning new technologies, and excellent communication skills in English are crucial attributes for success in this role. Joining the global team at Synopsys, you will contribute to the advancement of state-of-the-art high-performance cores and IPs implementation. Working with industry-leading tools and technologies, you will be part of a team focused on developing innovative methodologies to implement CPUs/GPUs and interface IPs efficiently. Your role will involve tackling complex design challenges, improving PPA metrics, and achieving best-in-class targets, thereby contributing to the continuous enhancement of Synopsys" technological capabilities.,

As a Principal Product Engineer at Cadence, you will be a part of a team that is at the forefront of electronic design, leveraging over 30 years of computational software expertise to transform design concepts into reality. You will have the opportunity to work with the world's most innovative companies, contributing to the development of extraordinary electronic products across various dynamic market applications such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health sectors. Cadence offers a stimulating work environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the physical and mental well-being of our workforce, support career development, provide continuous learning opportunities, and recognize and celebrate individual and collective successes. Our unique "One Cadence - One Team" culture emphasizes collaboration both within and across teams to ensure customer success. In this role, you will work with a diverse and passionate team of individuals who are dedicated to exceeding customer expectations and making a difference every day. Cadence provides numerous avenues for personal and professional growth, regardless of where you are in your career journey. To excel in this position, you should have a solid understanding of Hardware Description Languages (HDL) such as Verilog, System Verilog, and VHDL, along with experience in logic synthesis tools. Proficiency in timing concepts, SDCs, PPA push and analysis, 1801/UPF concepts, awareness of P&R flows, and power analysis and optimization would be advantageous. The ideal candidate should hold a BE/BTech/ME/MS/MTech degree or equivalent qualification. If you are looking to be part of a team that is committed to solving challenging problems and making a meaningful impact, Cadence is the place for you. Join us in our mission to tackle what others cannot.,

The job located at Bhosari MIDC, Pune is a Full Time position which involves project management for the entire project life cycle including design, testing, development, and manufacturing of smart electronic products. The role requires finalization of BOM, schematic, and PCB design, along with coordination with embedded hardware/software and mechanical design teams. Additionally, providing training to the electronic team on product features, technology, and services is essential. Encouraging and maintaining good practices and standards for long-term maintainability of code and hardware designs is also a key responsibility. Developing and installing product testing setups for electronics systems is part of the job profile. The ideal candidate should hold a BE/ME/MTECH degree in E&TC with 5 to 10 years of experience in product design and development. Strong expertise in embedded systems, including hardware and software, is required. Proficiency in C programming and debugging is desirable. Candidates should have a minimum of 3+ years of experience in project planning and team management. Knowledge of EMI/EMC, testing standards, and experience in interacting with testing labs would be advantageous, though not mandatory. Familiarity with power optimization techniques for low power devices is preferred. Technical leadership skills, effective communication, good team collaboration, and excellent analytical abilities are also essential qualities for this role. Candidates who meet the above criteria are encouraged to apply for this position. All Offer Letters and Appointment Letters are exclusively issued from the HEAD OFFICE under the signature of the GM Operations and are couriered from the HO. It is important to note that these letters are never issued by hand or given directly across the table from any factory or sales location. For more information or to apply, please contact [email protected],

As an Electronics Embedded Engineer, you will have the opportunity to work with Eeki (One of Uplers" Clients) in an office setting located in Kota. You will play a vital role in designing and testing embedded hardware interfaces for sensors and communication modules. Your responsibilities will include developing Product Requirement Documents (PRDs), system architecture, and supporting documentation throughout the product development lifecycle. You will be involved in schematic design, PCB layout, component selection, Bill of Materials (BOM) creation, Gerber file generation, and managing PCB manufacturing and assembly. Additionally, you will oversee board bring-up activities, manage vendors, handle import logistics for electronic components, plan project budgets, define test strategies, design custom test jigs, and manage product certification processes. The ideal candidate must possess skills in UART, Embedded Linux, SPI, I2C, Raspberry Pi, Eagle, and developing Product Requirement Documents (PRDs). You should also have experience in PCB bring-up, debugging, and validation, power optimization, signal integrity, and hardware integration of edge AI systems. Proficiency in schematic and PCB design tools such as Altium Designer, KiCAD, and Eagle is required for this role. In addition, there is an opportunity for a Manufacturing & Field Deployment Lead position where you will be responsible for developing low-level firmware for precise control and interfacing of sensors and camera modules. You will optimize and deploy edge machine learning (ML) models on embedded platforms like NVIDIA Jetson Nano and Raspberry Pi. Managing hardware interfaces for wireless connectivity, implementing Over-The-Air (OTA) update mechanisms, and designing strategies for efficient power management across edge computing systems and sensor networks are also crucial aspects of this role. To apply for this opportunity, follow the easy 3-step process: 1. Click on Apply! and register or log in on the portal. 2. Upload your updated resume and complete the screening form. 3. Increase your chances of getting shortlisted and meeting the client for an interview. If you are passionate about your work, eager to learn and grow, and committed to delivering exceptional results in the field of Electronics Embedded Engineering, this is the perfect opportunity for you. Join Eeki and be a part of a dynamic team that values innovation and excellence. Apply today and take your career to the next level with Uplers!,

As an Electronic Embedded Engineer at Eeki, you will be responsible for designing and testing embedded hardware interfaces for sensors and communication modules. Your key duties will include developing Product Requirement Documents (PRDs), system architecture, and supporting documentation throughout the product development lifecycle. You will also be involved in schematic design, PCB layout, component selection, Bill of Materials (BOM) creation, Gerber file generation, and managing PCB manufacturing and assembly. Additionally, you will oversee board bring-up activities, manage vendors, handle import logistics for electronic components, plan project budgets, define test strategies, design custom test jigs, and manage product certification processes. To excel in this role, you must possess skills in UART, Embedded Linux, SPI, I2C, Jetson Nano, Raspberry Pi, Altium Designer, KiCAD, Eagle, and developing PRDs. Your qualifications should include expertise in embedded Linux, PCB bring-up, debugging, validation, power optimization, signal integrity, and hardware integration of edge AI systems. Familiarity with schematic and PCB design tools such as Altium Designer, KiCAD, and Eagle is essential. Furthermore, as a Manufacturing & Field Deployment Lead, you will be responsible for developing low-level firmware for precise control and interfacing of sensors and camera modules. Your role will involve optimizing and deploying edge machine learning (ML) models on embedded platforms, managing hardware interfaces for wireless connectivity, implementing Over-The-Air (OTA) update mechanisms, and designing strategies for efficient power management across edge computing systems and sensor networks. To succeed in this position, you should have proficiency in C/C++ for embedded firmware, edge ML frameworks (TensorRT, OpenCV, PyTorch Lite), connectivity protocols (MQTT, HTTP, custom serial protocols), OTA frameworks, and power profiling techniques. The roles are based in Kota, Rajasthan, with a salary range of INR 4-6 LPA. The working hours are Monday to Saturday from 10 am to 6 pm. To apply for these opportunities, click on Apply! on the portal, register or login, complete the Screening Form, and upload your updated resume to increase your chances of getting shortlisted for an interview. Uplers is dedicated to simplifying and expediting the hiring process, providing support to all talents in finding and applying for relevant contractual onsite opportunities to advance their careers. If you are seeking a new challenge, a supportive work environment, and a chance to elevate your career, apply today and seize the opportunity to grow with us.,

As a member of the APPS Power Optimization Team, you will contribute to the optimization of power consumed by various test cases for upcoming Snapdragon SoCs designed for mobile, IoT, Wear, AR/VR, and modem products. Working alongside engineers from diverse disciplines such as hardware, software, and systems, you will engage with a wide range of technologies including advanced CPUs, Hexagon DSPs, Adreno GPUs, IoT, AR/VR, ML/AI, Wireless LAN, GPS, low power audio, and low power sensors. Your responsibilities will include debugging and analyzing high power issues in APPS SW, finding solutions to system-level power and resource management problems, and influencing hardware design to enhance power consumption efficiency. You will conduct hands-on performance, power, and thermal studies to optimize SW power, communicate experimental results effectively, review with technical leads and peers, and analyze outstanding issues. Collaboration with software teams to gather requirements and provide guidance on modules that interact with power and resource management software will be essential. Moreover, you will work with software teams to identify and rectify performance bottlenecks that lead to increased power consumption. Designing tools to pinpoint and resolve power consumption issues on development platforms and commercial devices will be a part of your role, along with inventing and filing patents for technical solutions to relevant problems.,

As a Senior System Embedded Engineer at Omnipresent Robot Tech Pvt. Ltd., you will be a key player in our satellite-based Dfense project, focusing on solution integration, system design, and cross-functional management. You will have the opportunity to work in a startup culture that values creativity and innovation. Your responsibilities will include architecting onboard AI-based change detection systems, researching space-grade SoCs, FPGAs, and computing platforms, seamlessly integrating SoCs, sensors, AI algorithms, and embedded systems, implementing sensor fusion for enhanced data accuracy, optimizing AI models for real-time execution, analyzing power, thermal, and computational constraints, testing AI workloads on multiple platforms for efficiency, coordinating with developers, engineers, and AI specialists, ensuring compliance with space-grade standards, and managing timelines and cross-functional collaboration. To qualify for this role, you should have a Bachelors's degree in Computer Science/Engineering (Masters a plus), along with 5+ years of experience in AI-driven embedded systems and automation. Expertise in system architecture, space-grade SoCs, and real-time data processing is required. Proficiency in Python, C++, and embedded programming is essential, as well as knowledge of radiation-hardened electronics and aerospace standards. Strong analytical, problem-solving, and collaboration skills are also expected.,

The Automotive Platform Architect position in Qualcomms central Platform Architecture team is a key role that involves defining common platform architectures and architecture features for the next-generation system-on-chip (SoC) products across Qualcomms business lines. This role specifically focuses on the Automotive business line, which includes areas such as In-vehicle Infotainment (IVI), the Digital Cockpit, Advanced Driver Assistance Systems (ADAS), and Autonomous Driving (AD). As an Automotive Platform Architect, you will have the opportunity to significantly impact the development of SoC architecture for the rapidly growing Automotive business. To qualify for this role, a Bachelor of Science degree in EE/ECE/CE/CS or a related field is required, with an MS or PhD highly desired. The ideal candidate should have experience in Automotive SoC architecture and automotive platform design, along with a deep technical background and credibility. Strong collaboration and influencing skills across various organizations, excellent communication, and interpersonal skills are essential. A commitment to integrity in all interactions is also expected. In this role, you will work closely with Qualcomms core SoC Hardware, Software, and Product Management teams, as well as the Automotive Business Unit, to develop scalable and reusable SoC architecture and features. You will contribute to the efficient development of cutting-edge SoC products for the Automotive business line, focusing on areas like IVI, Digital Cockpit, ADAS, and Autonomous Driving. This position offers a high level of visibility and the opportunity to shape Qualcomm's technical direction, drive innovation in the Automotive SoC industry, and make a significant impact on a global scale. Your responsibilities may include collaborating with Automotive Business Unit engineering leadership, translating product requirements into platform architecture requirements, defining the integration of Automotive SoCs into Qualcomm's overall SoC architecture platforms, and working on feature development to support Automotive SoCs. You will also evaluate architecture proposals, engage with core IP and component suppliers, and represent Qualcomm in customer meetings with technical expertise. Additionally, you will provide leadership in aligning hardware, software, and SoC organizations towards common architecture and technology goals, as well as drive the development of technical solutions and innovations. Minimum qualifications for this role include a Bachelor's degree in Electrical or Computer Engineering, Computer Science, or a related field. Ideal candidates will have 20+ years of work experience in SoC HW VLSI design/validation domains, with at least 7 years specifically in SoC Architecture. Preferred qualifications include a Master's degree in Electrical/Electronics engineering. Candidates with expertise in areas such as SoC/Computer Architecture, power and performance optimization, software engineering, digital hardware design, automotive domain architectures, safety standards, operating systems, machine learning, and various automotive interfaces and protocols will be highly valued for this role. Strong skills in HW engineering, caches, DSP architectures, memory management, and microprocessor systems design are also desirable. If you are a qualified candidate with a passion for shaping the future of Automotive SoC architecture and driving innovation in the Automotive industry, this role offers a unique opportunity to make a significant impact and contribute to Qualcomm's success.,

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

You will be responsible for software and system design, development, performance, and power optimization of XR products created using Qualcomm's industry-leading SoC on Android and Linux platforms. Your role will involve analyzing and decomposing complex software systems, collaborating with others, and influencing to enhance the overall design. You will need to be hands-on and provide technical leadership to a team of engineers. You should have a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field along with 2+ years of experience in Software Engineering. Alternatively, a Master's degree with 1+ year of experience or a PhD in a related field would be suitable. You need to have 2+ years of academic or work experience with programming languages like C, C++, Java, Python, etc. With 3-8 years of hands-on experience in designing and developing multimedia software at the Drivers, Middleware, Frameworks level in domains such as Virtual/Augmented Reality, Camera, Graphics, Video, Display, and Computer Vision, you should be proficient in C/C++ programming. Experience in embedded multimedia product development in Android Smartphones, Network-based Video, or Camera products is required. Knowledge of the internals of Linux and Android is essential. A Bachelor's or Master's degree in electrical & computer engineering or a related discipline from top institutes is preferred. Additional qualifications such as software development experience on heterogeneous/multi-core architectures, direct experience in XR product development, or previous development experience on Qualcomm Snapdragon platforms are advantageous. Candidates with apps and gaming development experience are least preferred. Qualcomm is an equal opportunity employer and provides accommodations for individuals with disabilities during the application/hiring process. Employees are expected to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is for individuals seeking jobs directly at Qualcomm, and submissions from staffing/recruiting agencies or individuals represented by agencies will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. For further information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a Software Engineer to contribute to the design, development, performance optimization, and power efficiency of XR products utilizing Qualcomms cutting-edge SoC technology on Android and Linux platforms. You will be tasked with analyzing complex software systems, collaborating with team members, and providing technical leadership. To qualify for this role, you should possess a Bachelor's, Master's, or PhD degree in Engineering, Information Systems, Computer Science, or a related field. Additionally, you should have at least 2 years of Software Engineering experience with programming languages like C, C++, Java, Python, etc. and 3-8 years of hands-on experience in multimedia software design and development in domains such as Virtual/Augmented Reality, Camera, Graphics, Video, Display, or Computer Vision. The ideal candidate should excel in C/C++ programming, have experience in embedded multimedia product development for Android Smartphones or Network-based Video/Camera products, and be familiar with the internals of Linux and Android systems. Candidates with additional qualifications such as expertise in heterogenous/multi-core architectures, XR product development, or previous experience with Qualcomm Snapdragon platforms will be preferred. Qualcomm values diversity and is an equal opportunity employer. If you require accommodations during the application process, Qualcomm is committed to providing accessible solutions. Please contact disability-accomodations@qualcomm.com for assistance. Qualcomm also expects its employees to adhere to all policies and procedures, including safeguarding confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing agencies and their representatives are not permitted to submit profiles, applications, or resumes through the site. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, reach out to Qualcomm Careers directly.,

Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience. 5 years of experience with thermal product design. Experience with programming/scripting with Python and MATLAB to develop in-house tools for data processing and automation. Experience working with heat transfer, SoC Design and IC Packaging. Preferred qualifications: Master's degree in Computer Science, Electrical Engineering, or a related field. Experience with optimization of thermal, power and performance. Experience in thermal/performance measurements and characterization on consumer devices. Understanding of ASIC digital design, design validation, and power optimization. Knowledge of hardware and software based thermal/power management control algorithms. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Thermal Engineer, you will be responsible for thermal modeling, analysis and characterization of various aspects of SoC and IC package thermal design. In this role, you will be delivering exceptional silicon for a wide range of applications and experiences and you will be working closely with teams across multiple functions to solve power and thermal related challenges. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Develop detailed Computational Fluid Dynamics (CFD) and compact RC models for SoC and Package thermal analysis. Place temperature sensors and optimize floor plans. Optimize thermal performance under Performance, Power, Area (PPA) and system design constraints. Simulate and prototype thermal control strategies. Validate thermal models through power/thermal measurements on hardware. ,