54 Power Optimization Jobs

About the Role We are looking for a passionate and detail-oriented Physical Design Engineer to join our VLSI design team. The ideal candidate will be responsible for implementing RTL to GDSII, optimizing performance, power, and area, and ensuring high-quality physical designs for advanced semiconductor technologies. Key Responsibilities Perform RTL-to-GDSII flow implementation including synthesis, floorplanning, placement, CTS, routing, and sign-off. Handle timing closure , power optimization , and design rule checks (DRC/LVS) . Work closely with RTL design, verification, and STA teams to meet PPA (Power, Performance, Area) goals. Support EDA tool flow setup , scripting, and automation to im...

As a highly experienced Firmware Engineer with 8+ years of hands-on experience in embedded audio software development, you will play a critical role in our hardware-software co-development team. Your expertise will directly impact the performance and user experience of our AR/VR smart glasses and immersive systems. You will collaborate closely with hardware, product, and design teams to drive the core embedded intelligence of our next-generation devices. **Key Responsibilities:** - Develop and optimize embedded audio firmware using C/C++, ensuring efficient performance, low power consumption, and real-time audio processing. - Work on Bluetooth audio protocols (A2DP, AVRCP, HFP), BLE profiles...

As an SSD Developer at Leadsoc Technologies in Hyderabad, you will play a crucial role in optimizing DDR/LPDDR performance and power for various use cases. Your responsibilities will include collaborating with internal and external development engineers, analyzing product-level system power and performance, and contributing to development, device characterization, and benchmarking efforts. Key Responsibilities: - Possess extensive experience in DDR/LPDDR system - Demonstrate proficiency in developing DDR/LPDDR memory controller - Have a deep understanding and extensive experience in working with JEDEC specifications for DDR/LPDDR - Exhibit comprehensive knowledge and experience in the embedd...

As an experienced chip design engineer, you will be responsible for the following key domains: - Power Optimization: Utilize low-power design techniques and methodologies, including expertise in the Unified Power Format (UPF). - Timing Optimization: Demonstrate proficiency in static timing analysis (STA) and implement design constraints using the Synopsys Design Constraints (SDC) format. - Functional Safety Analysis: Apply a deep understanding of functional safety concepts and standards (e.g., ISO 26262), employing analysis techniques such as FMEDA and FTA. - Utilize industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys, Cadence, or Siemens EDA. - Proficiency ...

As a highly experienced Firmware Engineer with 8+ years of hands-on experience in embedded audio software development, including Bluetooth audio, low-power design, and audio signal processing, you will play a critical role in our hardware-software co-development team. Your expertise will directly impact the performance and user experience of our AR/VR smart glasses and immersive systems. **Key Responsibilities:** - Develop and optimize embedded audio firmware using C/C++, ensuring efficient performance, low power consumption, and real-time audio processing. - Work on Bluetooth audio protocols (A2DP, AVRCP, HFP), BLE profiles (HAP, TMAP, HAS, PBP), and audio codec integration (SBC, AAC, aptX,...

As an experienced candidate with 6 to 15 years of experience, you will be responsible for the following: - Architecture, Micro-Architecture, Design, and RTL development for storage controller IP's based on UFS, NVMe, SAS, NVMeOF, eMMC, and high-speed peripheral bus standards such as PCIe. - Interfacing with cross-functional teams like Verification, Validation, and FW to ensure seamless collaboration. - Ensuring the quality of design by conducting Lint and CDC checks. - Synthesis, Area, and power optimization to enhance the performance of the storage controllers. - Developing timing constraints (SDC) and ECO scripts to streamline the design process and ensure quality deliverables and reuse. Y...

7-10 years of hands-on experience in block-level PnR and physical verification. Proficiency in tools such as Innovus, ICC2,Primetime,Calibre,or equivalent. Strong understanding of timing closure, power optimization, and signal integrity. Required Candidate profile Notice Period (Availability) - Immediate to 15 Days . Excellent analytical and debugging skills.

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. - Developing innovative methodo...

As a Senior Hardware Design Engineer, you will be responsible for designing and developing high-performance electronic hardware using advanced microcontrollers. Your key responsibilities will include: - Designing and developing high-performance electronic hardware using advanced microcontrollers. - Creating schematics and PCB layouts for multi-layered boards, ensuring signal integrity and power optimization. - Working extensively with Altium Designer for schematic capture, PCB layout, and BOM management. - Performing hardware simulation, testing, debugging, and validation. - Ensuring compliance with EMI/EMC standards and industry regulations. - Working on design for manufacturability (DFM) a...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

As a Systems Engineer working on Qualcomm Snapdragon SoC HW performance with High Level OS like Windows and Linux, your role overview includes conducting comprehensive performance benchmarking, analyzing and optimizing power and performance of gaming CPUs, GPUs, and other compute components, developing and implementing power management strategies, performing detailed system analysis, collaborating with hardware and software development teams, developing test plans, determining relevant KPIs, conducting deep dive analysis on performance issues, and interfacing with subsystem validation and SW teams during debugs. Key Responsibilities: - Conducting comprehensive performance benchmarking using ...

Skills Proficiency in C/C++ for embedded systems development. Strong understanding of embedded system architectures(e.g. STM family), especially MCUs (ARM, 32bit, 8 bit, 16 bit, DSP, etc.) Experience with real-time operating systems (RTOS) and bare-metal systems. Strong understanding of communication protocols like SPI, I2C, UART, MODBUS, and CAN. Familiarity with development and debugging tools like JTAG, GDB, Eclipse, STMCUBEIDE, and Keil. Experience with peripheral integration (GPIO, timers, ADCs, DACs, etc.) Basic understanding of memory and power optimization Experience with JIRA, Git, and Bitbucket Good to have: experience in Camera domain (ISP pipelines) Key Responsibilities Design an...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Soc Design Architect The Role We are seeking a seasoned SoC Design Lead with expertise or s...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences - from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. T...

Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers , collaborate with cross-functional teams, and ensure the successful implementation of high-performance, low-power designs. The ideal candidate should have a strong technical background in RTL design , experience in digital design flow , and the ability to lead a team towards the successful execution of complex projects. Key Responsibilities: RTL Architecture and Design: Lead the RTL design of complex digital systems, including microprocessors , ASICs , FPGA designs , and system-on-chip (SoC) compon...

Job Title : Physical Design Engineer Location State : Maharashtra Location City : Pune Experience Required : 5 to 10 Year(s) Shift: Day Shift Work Mode: Hybrid Position Type: Permanent Openings: 1 Company Name: VARITE INDIA PRIVATE LIMITED About The Client: VARITE is a global staffing and IT consulting company providing technical consulting and team augmentation services to Fortune 500 Companies in USA, UK, CANADA and INDIA. VARITE is currently a primary and direct vendor to the leading corporations in the verticals of Networking, Cloud Infrastructure, Hardware and Software, Digital Marketing and Media Solutions, Clinical Diagnostics, Utilities, Gaming and Entertainment, and Financial Servic...

About Viyona Fintech : At Viyona Fintech, we are building next-generation financial solutions that merge fintech innovation and embedded systems. Our products, including Viyona Pay and GraamPay, are designed to revolutionize financial transactions by bridging the gap between traditional and digital banking. Role Overview: We are seeking a highly motivated Embedded Systems Engineer with strong expertise in f irmware development, sensor integration, and power optimization . The ideal candidate will work on low-power IoT payment devices and ensure seamless hardware-software integration for secure financial solutions. Note : Immediate Joiners are more preferable Key Responsibilities: Develop, te...

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the ...

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....

Role Overview: As the ASIC Back-End Head at Wipro Limited, your primary responsibility will be to lead the physical design and implementation of Application-Specific Integrated Circuits (ASICs). You will be tasked with ensuring optimal performance, power efficiency, and manufacturability of ASICs. Key Responsibilities: - Define and execute the ASIC back-end design roadmap with a strategic approach. - Oversee the RTL to GDSII flow management, including synthesis, floorplanning, placement, routing, timing closure, and sign-off. - Ensure Physical Design Optimization by meeting Power, Performance, and Area (PPA) targets. - Utilize EDA Tool Expertise by working with Synopsys, Cadence, and Mentor ...

As a Cellular RF Software/Firmware Engineer, you will play a crucial role in the embedded 5G/4G/multimode cellular firmware effort within a silicon design group. Your responsibilities will include: - Specify, design, and implement the physical layer embedded software architecture for a mobile wireless communications system. - Design, develop, and optimize Cellular Processing algorithms for Baseband and RF components in a cellular system. - Implement RF Control software in the baseband modem with precise timing requirements. - Collaborate with Baseband & RF systems and hardware designers to define hardware function and software computing requirements. - Optimize power consumption for all RF c...

You are a highly skilled and experienced Full Chip RTL Design Architect sought by the company to join their dynamic team. Your role involves a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. You will be pivotal in defining and implementing full chip-level RTL designs to ensure successful execution. - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications and ensure seamless implementation. - Develop and opt...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated R&D Engineer with a deep understanding of physical design and a knack for solving complex design challenges. With a strong background in place & route, timing closure, and power optimization, you thrive in dynamic environments where technological...

As an IoT Engineer at Kalkey, you will play a crucial role in redefining the future of IoT by working on cutting-edge IoT hardware. Your responsibilities will include: - Hardware Development & Design: - Creating custom PCB layouts using Altium, KiCad, or Eagle - Sourcing optimal sensors, microcontrollers, and components - Drafting detailed schematics and maintaining library databases - Optimizing designs through Design for Manufacturability (DFM) practices - Firmware & Communication Protocols: - Developing and testing embedded firmware in C/C++ - Implementing MQTT and secure IoT communication stacks - Configuring WiFi, Bluetooth, LoRaWAN, and cellular connectivity - Applying encryption and c...