1.0 - 4.0 years

1 - 3 Lacs

Hyderabad, Chennai, Bengaluru

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VLSI Design Engineer Job Title : VLSI Design Engineer Location : Chennai, Hyderabad, Bangalore Experience : 1-4 Overview: Works on the design and verification of integrated circuits (ICs), including ASICs and FPGAs, for high-performance applications. Key Responsibilities: RTL design using Verilog/VHDL. Functional verification and synthesis. Timing analysis and power optimization. Collaborate with layout and physical design teams. Tools & Technologies: Synopsys Design Compiler, Cadence Virtuoso Model Sim, Viva do, Quartus Verilog, VHDL Career Path: VLSI Lead Chip Design Architect Semiconductor R&D Manager

Posted 2 months ago

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Staff IP Physical Design Engineer Qualcomm

3.0 - 7.0 years

5 - 8 Lacs

Bengaluru

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Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc.

Posted 3 months ago

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