65 Power Optimization Jobs - Page 2

Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers , collaborate with cross-functional teams, and ensure the successful implementation of high-performance, low-power designs. The ideal candidate should have a strong technical background in RTL design , experience in digital design flow , and the ability to lead a team towards the successful execution of complex projects. Key Responsibilities: RTL Architecture and Design: Lead the RTL design of complex digital systems, including microprocessors , ASICs , FPGA designs , and system-on-chip (SoC) compon...

Job Title : Physical Design Engineer Location State : Maharashtra Location City : Pune Experience Required : 5 to 10 Year(s) Shift: Day Shift Work Mode: Hybrid Position Type: Permanent Openings: 1 Company Name: VARITE INDIA PRIVATE LIMITED About The Client: VARITE is a global staffing and IT consulting company providing technical consulting and team augmentation services to Fortune 500 Companies in USA, UK, CANADA and INDIA. VARITE is currently a primary and direct vendor to the leading corporations in the verticals of Networking, Cloud Infrastructure, Hardware and Software, Digital Marketing and Media Solutions, Clinical Diagnostics, Utilities, Gaming and Entertainment, and Financial Servic...

About Viyona Fintech : At Viyona Fintech, we are building next-generation financial solutions that merge fintech innovation and embedded systems. Our products, including Viyona Pay and GraamPay, are designed to revolutionize financial transactions by bridging the gap between traditional and digital banking. Role Overview: We are seeking a highly motivated Embedded Systems Engineer with strong expertise in f irmware development, sensor integration, and power optimization . The ideal candidate will work on low-power IoT payment devices and ensure seamless hardware-software integration for secure financial solutions. Note : Immediate Joiners are more preferable Key Responsibilities: Develop, te...

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the ...

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....

Role Overview: As the ASIC Back-End Head at Wipro Limited, your primary responsibility will be to lead the physical design and implementation of Application-Specific Integrated Circuits (ASICs). You will be tasked with ensuring optimal performance, power efficiency, and manufacturability of ASICs. Key Responsibilities: - Define and execute the ASIC back-end design roadmap with a strategic approach. - Oversee the RTL to GDSII flow management, including synthesis, floorplanning, placement, routing, timing closure, and sign-off. - Ensure Physical Design Optimization by meeting Power, Performance, and Area (PPA) targets. - Utilize EDA Tool Expertise by working with Synopsys, Cadence, and Mentor ...

As a Cellular RF Software/Firmware Engineer, you will play a crucial role in the embedded 5G/4G/multimode cellular firmware effort within a silicon design group. Your responsibilities will include: - Specify, design, and implement the physical layer embedded software architecture for a mobile wireless communications system. - Design, develop, and optimize Cellular Processing algorithms for Baseband and RF components in a cellular system. - Implement RF Control software in the baseband modem with precise timing requirements. - Collaborate with Baseband & RF systems and hardware designers to define hardware function and software computing requirements. - Optimize power consumption for all RF c...

You are a highly skilled and experienced Full Chip RTL Design Architect sought by the company to join their dynamic team. Your role involves a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. You will be pivotal in defining and implementing full chip-level RTL designs to ensure successful execution. - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications and ensure seamless implementation. - Develop and opt...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated R&D Engineer with a deep understanding of physical design and a knack for solving complex design challenges. With a strong background in place & route, timing closure, and power optimization, you thrive in dynamic environments where technological...

As an IoT Engineer at Kalkey, you will play a crucial role in redefining the future of IoT by working on cutting-edge IoT hardware. Your responsibilities will include: - Hardware Development & Design: - Creating custom PCB layouts using Altium, KiCad, or Eagle - Sourcing optimal sensors, microcontrollers, and components - Drafting detailed schematics and maintaining library databases - Optimizing designs through Design for Manufacturability (DFM) practices - Firmware & Communication Protocols: - Developing and testing embedded firmware in C/C++ - Implementing MQTT and secure IoT communication stacks - Configuring WiFi, Bluetooth, LoRaWAN, and cellular connectivity - Applying encryption and c...

As an Embedded Firmware IoT Intern at AriveGuru Technology Solutions Pvt. Ltd, you will have the opportunity to work on real-world projects focused on robotics, automation, and intelligent devices, collaborating with the R&D and product engineering teams. This internship provides a hands-on experience in the full product lifecycle development, utilizing the latest microcontroller technologies and IoT frameworks. Key Responsibilities: - Design, develop, and optimize firmware in C/C++ or MicroPython for ARM Cortex-M-based microcontrollers like ESP32 and STM32. - Interface and integrate digital and analog modules (sensors, actuators) over UART, SPI, I2C, and GPIO. - Work closely with the hardwa...

As a member of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. **Key Responsibilities:** - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Carry out Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in ...

As a SoC Power Management Design Engineer at AMD, your role will involve developing and designing custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. You will collaborate with the lead SoC architect to define customer-specific architectures, contribute to product specifications, and make performance and power trade-offs. Your work will span from early concept development through final production, requiring excellent organization and communication skills. You will work with expert architects and designers globally, presenting your findings to colleagues and customer engineering teams. Key Responsibilities: - Drive physical design and...

Embedded Firmware Engineer with expertise in C/C++, CAN/ethernet, Cortex M4, debugging & protocol integration. Responsible for design, coding, testing & optimization of embedded systems. Required Candidate profile BE/BTech/ME/MTech in Electronics with 3–7 yrs exp in Embedded C/C++, CAN, Cortex M4, UART, SPI, I2C. Skilled in debugging,interrupt-based design,RTOS,Modbus & wireless tech Self-starter,problem-solver

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the ...

The ASIC Design Senior Engineer plays a critical role in the development and implementation of advanced integrated circuit designs within the organization. You will be instrumental in driving innovation and ensuring that the products maintain a competitive edge in the rapidly evolving semiconductor industry. Your responsibilities will include contributing technical expertise and leadership in the ASIC design process, from initial concept through to production. Working collaboratively with cross-functional teams, you will solve complex design challenges, optimize performance, and ensure adherence to industry standards. In addition to deep technical knowledge, this role will require the abilit...

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexiti...

The Android Automotive Lead role requires 5-10 years of experience in the relevant field and a BE, B.Tech / ME, M.Tech educational qualification. This position is based in Bangalore. As an Android Automotive Lead, you will need to demonstrate expertise in Android Dev, Android NDK, C/C++/Java, and Automotive Domain. Your responsibilities will include: - Proficiency in Android-Auto, AOSP Framework, Framework Optimization, IPCs, and android ecosystems. - Knowledge of Android, Linux, and QNX middleware/frameworks, MM HALs such as Audio, Video, Camera, Display, Graphics, and AI. - Development skills in Android, Linux, and QNX frameworks, as well as experience with Hypervisors, Virtual Machines (V...

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Role Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area / power / performance / convergence) , develop plans and deploy/support them Powe...

You will be responsible for designing and optimizing memory architectures for high-performance and low-power applications as a skilled SRAM & ROM IC Memory Design Engineer. Your main tasks will include designing, simulating, and verifying SRAM and ROM memory blocks while collaborating with cross-functional teams in circuit design, layout, verification, and technology development. Key responsibilities for this role include designing and developing SRAM and ROM memory architectures for various semiconductor applications, performing transistor-level circuit design and simulation, optimizing power, performance, and area (PPA) of memory designs, conducting timing, reliability, and variation analy...

As an experienced professional in the field of semiconductor design, you will be involved in working on advanced technology nodes such as 7nm/5nm or lower, collaborating closely with a diverse range of customers to deliver cutting-edge solutions. Your role will primarily revolve around addressing and resolving critical design issues to meet performance, area, and power requirements. One of your key responsibilities will be to develop innovative flows and methodologies for efficient placement, clock tree synthesis (CTS), and routing. Your expertise in these areas will be instrumental in ensuring the successful implementation of complex designs and meeting project goals effectively. Additional...