SOC DFT Lead/Manager

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation. Key Responsibilities: - Develop logic design, RTL coding, simulation, and provide DFT timing closure support - Generate test content for various DFx content including SCAN, MBIST, and BSCAN - Collaborate in defining architecture and microarchitecture features - Write and generate RTL and structural code to integrate DFT - Optimize logic to meet design requirements - Review verification plan and drive verification of DFT design - Integrate DFT blocks into functional IP and SoC - Perform quality-related clean-ups and work with design teams for hand-over Qualifications: - Bachelor's in Electrical Engineering with 15+ years of experience, or Master's in VLSI with 10+ years of experience - Good working knowledge of scripting languages like Perl, Python is desired - Ability to drive overall DFX execution for an SoC is an added advantage - Minimum of 8 years in SCAN and TAP design (Note: No additional details of the company were present in the job description),