36 Ip Integration Jobs

Introduction As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market. We are looking for a DFT lead to join our dynamic team and drive excellence in chip test strategies, design and testability. Your Role And Responsibilities We are seeking highly motivated DFT Engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation and delivery of DFT patterns for IBM's chip design team. As a member of DFT team,...

You have a great opportunity as an RTL/FPGA Design Engineer with a minimum of 3-7 years of experience. Your role will involve RTL programming using Verilog/System Verilog or VHDL, knowledge of the complete FPGA Design Development flow, hands-on experience with FPGA Development Tools like Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will be responsible for functional verification using Verilog/System Verilog or VHDL, RTL Code Optimization to meet timings and fit on-chip resources, supporting all phases of FPGA based product development activities, system architecture design, and testing and troubleshooting of hardware. **Key Responsibilities:** - RTL programming using...

Role Overview: As a humble genius at Quest Global, you will lead the Full chip and Block level activities in the project. Your hands-on experience in full chip activities will be crucial in contributing to meaningful work and designing a brighter future for all. You will be part of a team of remarkably diverse engineers who believe in making the impossible, possible through engineering. Key Responsibilities: - Lead the Full chip and Block level activities in the project. - Hands-on experience in full chip activities. - Experience in Full Chip Integration activities such as Full Chip Floor Planning, Power Planning, Bus Planning, Full Chip timing, Full Chip Reliability, and Full Chip Physical ...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience worki...

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be an integral part of our culture that values passion for technology solutions impacting businesses. You will have the opportunity to pursue your individual passions while gaining a deep understanding of various industries and emerging technologies to build futuristic and impactful solutions. Working with us may even help you evolve personally towards a more fulfilling life. **Key Responsibilities:** - Possessing 10+ years of ASIC RTL Design experience with proficiency in Verilog/System Verilog - Demonstrating experience with multiple clock and power domains - Having extensive experience in the integration and validation of ...

Role Overview: As a Senior RTL Design Lead at Synopsys, you will play a crucial role in leading complex ASIC digital subsystems from concept to silicon. You will be responsible for crafting subsystem architectures, developing functional specifications, implementing micro-architectures, and ensuring compliance with best RTL coding practices. Your expertise in industry-standard protocols such as PCIe, DDR, UFS, USB, and AMBA will be essential in integrating them within subsystem designs. Additionally, you will mentor junior engineers, participate in technical reviews, and drive innovation within the team. Key Responsibilities: - Lead the complete subsystem lifecycle, from requirements gatherin...

Description Job Title: Director, HW Design Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office ) Job ID: AI2440 Job Description We are seeking a Design Team Manager to lead our SoC design team in Bangalore. This is a hands-on leadership role responsible for managing and scaling a team of front-end SoC design engineers, driving execution across multiple projects, and collaborating with cross-functional teams across architecture, verification, physical design, firmware, and software. You will play a pivotal role in defining, implementing, and delivering SiMa.ai's next-generation MLSoC designs. Areas Of Focus Lead a high-performing...

As a VLSI Engineer with 5-6 years of experience in the semiconductor industry, your role will involve working on complex SoC designs, collaborating with cross-functional teams, and delivering high-quality silicon solutions. Your key responsibilities will include: - Designing and developing RTL using Verilog / SystemVerilog for ASIC/FPGA. - Performing functional verification using UVM / SystemVerilog based testbench. - Working on synthesis, timing analysis, power analysis, and design for testability (DFT). - Collaborating with physical design, firmware, and validation teams to ensure design quality. - Understanding semiconductor process technologies and device physics. - Participating in desi...

As an ASIC/FPGA Designer, you will work closely with Algorithm and Architecture teams to understand and translate high-level algorithmic requirements into efficient hardware implementations. You will learn and analyze relevant protocols and standards, interpreting protocol specifications such as Ethernet, and applying them accurately in design. Your responsibilities will include: - Participating in all design stages, including micro-architecture definition, RTL coding (using Verilog/SystemVerilog/VHDL), and synthesis-friendly coding with timing-aware design. - Collaborating cross-functionally with the verification team for testbench development, debug support, and functional coverage closure...

As an ASIC Design Engineer at AMD, you will be part of the AMD IOHUB Team within the NBIO organization. Your primary responsibility will be to contribute to the development of cutting-edge I/O connectivity and virtualization technologies that power data center and machine learning workloads. This role involves working on various aspects of IP design, from architecture to execution. Your contributions will play a key role in ensuring the highest quality and industry-leading technologies are delivered to the market. Key Responsibilities: - Design complex IPs including control and datapath components. - Understand the functional and performance requirements of IOHUB in different SOCs. - Ensure ...

VLSI Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. ...

Job Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog . Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams. Requires strong fundamentals in digital design , timing closure, and understanding of the ASIC flow. You'll debug simulation failures, implement ECOs, and support gate-level simulations. Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals. Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevan...

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SMTS Verification Engineer to join our Security IP team in Bangalore, India . In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Lead MTS Verification Engineer, you'll play a pivotal role in the verification of secure ASIC cores developed by Rambus Security Division (RSD), working with cross functional teams including ASIC design engineers and architects, other verification engineers and system test engineers, security experts, and cryptographers. Cryptography and hardwa...

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point o...

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Role Overview: As a part of Micron Technology, you will play a crucial role in innovating memory and storage solutions, accelerating the transformation of information into intelligence. Your expertise in ASIC Physical Verification and overall design flow will be instrumental in achieving the best PPA for block/chip PV closure and ensuring DRC & LVS closure for complex hierarchical designs. Key Responsibilities: - Achieve block/chip PV closure to optimize PPA - Conduct DRC & LVS closure for block and full chip designs in 5nm/3nm nodes - Collaborate with IR, IP, ESD, and PD teams to ensure Physical Verification convergence - Work on multiple blocks simultaneously with minimal supervision - Ens...

Role Overview: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will collaborate with design experts to develop the best implementation methodologies and flows for the BE flows. Key Responsibilities: - Define and drive key Backend/Physical Design methodologies. - Collaborate with AMD CAD Teams, Design team, and physical design teams to ensure smooth end-to-end design flows. - Assist in defining roadmaps for existing flows and provide technical support for challenging technical debug. - Gather requirements from design teams and devise strategies to address critical technical issues. - Engage in Floor-plan, Physical Implementation of Power-plan, Synthes...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller an...

Job Overview As a part of in Arm&aposs Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Timing analysis and closur...

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture dia...

Role Overview: As a Senior FPGA Design Engineer at Axiado, you have the opportunity to join a leading company in platform security management and ransomware detection for cloud datacenters, 5G infrastructure, and disaggregated compute ecosystems. Your role will involve RTL design, FPGA prototyping, and computer architecture tasks. You will collaborate closely with various teams within the organization and contribute to the design, verification, debug, and system integration processes. Key Responsibilities: - RTL design for FPGA, including IP integration, closing timing, and generating bit streams - Conduct simulation testing - Set up FPGA systems - Validate and debug FPGA systems - Collabora...

At Synopsys, you will play a crucial role in driving innovations that have a significant impact on the way people live and connect. The technology developed by Synopsys is at the forefront of the Era of Pervasive Intelligence, contributing to advancements such as self-driving cars and learning machines. As a part of Synopsys, you will be part of a team that leads in chip design, verification, and IP integration, enabling the development of high-performance silicon chips and software content. By joining us, you will have the opportunity to be a part of transforming the future through ongoing technological innovation.,

As an experienced Digital Design Engineer with 3+ years of experience, you will collaborate with system architects to interpret high-level specifications and requirements for digital design. Your responsibilities will include creating RTL descriptions of digital circuits using hardware description languages such as Verilog and SystemVerilog to capture the desired functionality. You will implement digital logic functions, state machines, and control units to meet design goals for performance, power, and area (PPA). In this role, you will work with synthesis tools like Synopsys Design Compiler and Cadence Genus to optimize the RTL code for efficient gate-level implementation. You will address ...

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification us...

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. You...