7 Rtl Integration Jobs

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and Constraint development, debug designs in simulation environments, and have a deep understanding of fundamental concepts of digital design. Preferred skills for this role include strong Verilog/System Verilog RTL coding skills, experience with DRAM Memory Controller design, and knowledge of DRAM standard (DDR4/5) memory. Interface/Protocol experience required are AHB/AXI, Processor local bus, Flash, SPI, UART, etc. Experience with Xilinx/Intel FPGA Tool flow, knowledge of PCIe/PIPE, knowledge of projects with Microblaze, ARM cores, etc., and CXL Protocol knowledge is appreciated. To qualify for this position, you should have a Masters or Bachelors degree in Electronics or Electrical Engineering along with 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.,

As a Frontend Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, and project management skills. Additionally, you will oversee product support activities for both the Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. You should have a minimum of 8+ years of experience in System Architecture for ARM based MCU product development, along with a minimum of 8+ years of experience in RTL Design, Coding, and RTL Integration. Strong design and debugging skills are essential for this role. Experience in handling Verification Teams, including Verification environment Development, Static and Dynamic Verification, and Test Management (UPF, GLN, Test Mode) is required. It is important to have experience with industry-standard EDA tools for LINT, CDC, SDC validation, and power analysis, preferably Synopsis EDA. Exposure to Backend and Analog processes is a plus. You should have the ability to collaborate effectively with backend teams (PD, DFT, and STA) to achieve timing and power closure. Experience in Product Support for both Pre and Post Production Stages, as well as support for RMA teams, is also necessary. Preferred skills and experience include a minimum of 1+ years of Project Management (Waterfall and Agile Hybrid Methodology) and a focus on Continuous Improvement. Knowledge of industry standards and best practices in semiconductor front-end design is advantageous. Qualifications for this role include a Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field.,

NVIDIA, a company known for continuously reinventing itself, has played a pivotal role in reshaping the PC gaming market, modern computer graphics, and parallel computing with the invention of the GPU. The realm of artificial intelligence is currently experiencing significant growth globally, necessitating highly scalable and massively parallel computation capabilities where NVIDIA GPUs excel. NVIDIA's commitment lies in addressing challenging problems that have a profound impact on the world, ultimately aiming to enhance human creativity and intelligence. As part of the NVIDIA team, you will find yourself in a diverse and supportive environment that fosters inspiration and excellence, encouraging everyone to deliver their utmost potential. Join our team to leave a lasting imprint on the world! The NVIDIA System-On-Chip (SOC) group is seeking a talented Senior SOC Design Engineer to contribute to the development of complex chips that now incorporate tens of billions of transistors to meet the escalating computational demands. We are looking for a standout candidate with a strong affinity for RTL integration and chip-level front-end design, encompassing elements such as padring, pinmuxing, SOC Assembly process, retiming, and more. Your role will involve a genuine enthusiasm for methodologies and automation solutions that facilitate SOC creation in the most efficient manner. In this capacity, you will have the opportunity to participate in the construction of advanced Tegra SOCs, collaborating closely with chip management to establish ASIC execution timelines and objectives, while engaging directly with various teams including System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT, and others. Furthermore, you will contribute to defining and refining methodologies that will enable the development of more streamlined and adaptable SOCs in the future. **What you'll be doing:** - Drive SOC Assembly and design chip-level functions for Tegra SOCs. - Ensure front-end design quality and correctness through checks, reviews, and collaboration with multi-functional teams. - Lead SOC execution across chip milestones, working in coordination with various teams to define, track, and manage intricate dependencies. - Develop and implement system-level methodologies, tools, and IPs to streamline SOC development in an efficient and scalable manner. - Identify and address challenges and inefficiencies in the front-end chip implementation process, proposing and implementing solutions to enhance effectiveness. **What we need to see:** - B.Tech or M.Tech in Electronics Engineering. - 5+ years of demonstrated experience in chip design, with a focus on SOC integration and design automation. Knowledge of padring and fuse/floorsweep design is advantageous. - Strong analytical and problem-solving abilities. - Proficiency in RTL design (Verilog), System-On-Chip design/implementation flow. - Proficient in coding with Perl, Python, or other standard scripting languages. - Exposure to diverse Chip Design Functions to collaborate and resolve complex multi-functional challenges. - Excellent interpersonal skills to engage with multiple teams effectively and drive consensus. - Strong teamwork and collaboration skills with fellow team members. - Background in SOC Verification, Synthesis, Physical design, and DFT is a plus. - Experience in RTL Build flows and Makefiles is beneficial.,

You will be responsible for driving DFT implementation in Wireless SoC chips. You will have full ownership of ATPG architecture, design, implementation, verification, and deployment to Silicon testing, collaborating with Test engineers. Your duties will also involve MBIST design, implementation, and verification for all memories in the SoC. You should be capable of generating and debugging DFT patterns on the tester. You will work closely with the design, design-verification, and backend teams to facilitate the integration and validation of the test logic in all phases of the design and backend implementation flow. To excel in this role, you are required to have 8-10 years of experience and a B.Tech/M.Tech degree in ECE or EEE. You must possess full-chip DFT working experience with multiple design Tape Outs and expert knowledge of DFT architecture on complex Designs with multiple clock domains. Furthermore, experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults is essential. Hands-on experience in industry-standard DFT tools like Mentor Tessent suite or Synopsys DFT compiler is also a must-have. Your responsibilities will also include block-level and chip-level SCAN insertion, DRC, Coverage Analysis, and improvements. Expertise in Scan Compression (EDT/OPMISR+), MBIST, ATPG implementation, and verification is crucial. You should have expert knowledge of Test time reduction, good knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments & LEC. Developing/automating flows and scripts in Perl/Tcl to enhance the DFT methodologies & process is expected from you. Experience working with cross-functional global teams, Low-Power DFT requirements, and Low-Power MBIST architectures and Memory testing is also necessary. Preferred qualifications include experience in DFT related RTL integration, excellent communication and analytical skills, experience in leading junior teams, mentoring/training, and project leadership, as well as exceptional problem-solving skills. In addition to the challenging work environment, you can look forward to benefits such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans with Outpatient cover, National Pension Scheme (NPS), flexible work policy, and childcare support. Join us and be a part of a highly skilled team where every engineer's contribution significantly impacts the product, while also enjoying a good work/life balance and a welcoming and fun work environment.,

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

Good understanding of the ASIC flow and digital concepts RTL Designing knowledge with Verilog or System Verilog. Hands on experience in RTL integration Good knowledge and exposure to defining HW interfaces. Worked on Lint, CDC and RDC Good exposure on the RTL integration Strong programming suits various languages such as Verilog, C/C++, Python, Perl with a knack for problem-solving abilities. Experience working with ARM/RISC V processors Excellent written and verbal communication skills Fundamental understanding of Bus or Pin Planning, Block or Chip Level Floor planning, Clock Tree Synthesis, Static Timing Analysis, Knowledge on USB 3.1 or DDR protocol is plus Good knowledge on the verification concepts and run the regressions and analyze the failures. Skills Required Clock Tree Synthesis,DDR (Inactive),Python (Programming Language),Static Timing Analysis (STA),USB Protocol,SystemVerilog,Verilog,RTL Design,Processors Location Bengaluru, India Desirable Skills Clock Tree Synthesis,DDR (Inactive),Python (Programming Language),Static Timing Analysis (STA),USB Protocol,SystemVerilog,Verilog,RTL Design,Processors Designation Associate

We are looking for experienced RTL Integration Engineers to join our team and contribute to cutting-edge semiconductor designs. If you have a passion for SoC integration and front-end design methodologies, we want to hear from you! Key Responsibilities: Deliver RTL Subsystems and/or top-level SoC RTL across multiple projects Expertise in RTL database management, partitioning, and third-party IP integration Work with lint, DFT, UPF, synthesis, timing, and power analysis Address SoC integration challenges at both subsystem and full-chip levels Integrate Digital IPs such as PCIe, SDIO, USB, and ARM processors with protocol expertise Design top-level clock/reset circuits and manage memory selection/generation Join us and be part of a high-impact team shaping the future of semiconductor technology! Interested Drop your resume at info@silcosys.com #RTL #SoC #Integration #Semiconductor #Hiring #VLSI #Engineering #JobOpening,