RTL Design Engineer

• Good understanding of the ASIC flow and digital concepts
• RTL Designing knowledge with Verilog or System Verilog.
• Hands on experience in RTL integration
• Good knowledge and exposure to defining HW interfaces.
• Worked on Lint, CDC and RDC
• Good exposure on the RTL integration
• Strong programming suits various languages such as Verilog, C/C++, Python, Perl with a knack for problem-solving abilities.
• Experience working with ARM/RISC V processors
• Excellent written and verbal communication skills
• Fundamental understanding of Bus or Pin Planning, Block or Chip Level Floor planning, Clock Tree Synthesis, Static Timing Analysis,
• Knowledge on USB 3.1 or DDR protocol is plus
• Good knowledge on the verification concepts and run the regressions and analyze the failures.

Skills Required

Clock Tree Synthesis,DDR (Inactive),Python (Programming Language),Static Timing Analysis (STA),USB Protocol,SystemVerilog,Verilog,RTL Design,Processors

Location

Bengaluru, India

Desirable Skills

Clock Tree Synthesis,DDR (Inactive),Python (Programming Language),Static Timing Analysis (STA),USB Protocol,SystemVerilog,Verilog,RTL Design,Processors

Designation

Associate