Hands-on experience with SRAM, register files, ROM, TCAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc. Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory. Good hold on IR/EM related issues in memory layouts. Exp range : 5-8 Job Types: Full-time, Permanent Pay: ₹359,341.45 - ₹1,550,395.11 per year Work Location: In person
Good knowledge on the digital concepts and ASIC flowExperience in RTL coding is a must.Must have hands on experience with SoC design and integration.Experience in Verilog/System-Verilog is a must.knowledge of AMBA protocols - AXI, AHB, APBBasic knowledge on verificationUnderstanding of Memory controller designs and microprocessors is an added advantageExperience in Synthesis / Understanding of timing concepts is a plus.Excellent oral and written communications skillsProactive, creative, curious, motivated to learn and contribute with good collaboration skills. Mandatory Skills: Verilog,Synthesis (Inactive),Design,ASIC Flow,Static Timing Analysis (STA),RTL Design,RTL Coding Exp: 3to 5 Years Job Type: Full-time Work Location: In person