RTL Design Engineer

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and drive convergence. You will be responsible for setting up ASIC QA flows for RTL design quality checks, understanding top-level design interfaces, clock structures, and power domains, as well as running various design verification steps like Lint, Synthesis, Static timing analysis, CDC, RDC, DFT, and CLP. Your role will involve coming up with clock constraints, debugging design issues, supporting DFX team for integration tasks, handling multiple PNR blocks, and porting design to different technology libraries. Additionally, you will generate RAMs based on targeted memory compilers and run functional verification simulations as required. The ideal candidate for this role is passionate about modern processor architecture and digital design, with a strong background in ASIC design flow and direct experience in sub-20nm technology nodes. You should have experience with RTL design in Verilog/SystemVerilog and familiarity with modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal, and VCS simulation. Preferred qualifications include experience with AXI4 or NOC protocols, DRAM memory interfaces, and scripting languages like TCL, Perl, and Python. To qualify for this position, you should hold a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering with at least 5 years of relevant experience in the field. Candidates with project-level experience in design concepts, familiarity with formal tools, and good understanding of computer organization/architecture will be given preference. Join AMD in advancing next-generation computing experiences and be part of a culture that values innovation, execution excellence, and diversity. Apply now to contribute to building products that shape the future of technology and change lives with AMD technology.,