RTL Design Engineer

We’re Hiring: RTL Design Engineer (3+ Years) – Bangalore

Are you passionate about front-end design and ready to take the next big step in your VLSI career?

We’re looking for skilled RTL Design Engineers

🔧 Key Skills & Experience:

• 3–5 years of hands-on experience in

  ASIC front-end design and quality checks

• Strong fundamentals in Digital Design, Verilog

  , and

  Scripting (TCL/Perl/Python)

• Experience working with multiple clock and voltage domain designs

• Proficiency in FE flows

  such as Lint, CDC, Synthesis, and other quality checks
• Understanding of

  UPF

  and

  low-power checks

  (preferred)
• Knowledge of

  memory controllers, cache controllers, or memory subsystems

  is a plus
• Excellent communication skills; experience working with

  global teams

  preferred

• Education:

  B.Tech/B.E/M.Tech in Electronics or related field

🎯 Responsibilities:

• Perform

  RTL front-end quality checks

  (Lint, CDC, Synthesis, LEC, Low Power)
• Write and debug

  constraints

  for QA flows
• Collaborate with

  subsystem/SOC integration

  teams for design integration and debug
• Coordinate with

  cross-functional teams

  for smooth and timely project execution
• Support

  SoC integration, synthesis, DFT, and post-silicon debug

• Work effectively with global teams

  across time zones

Location:

Experience:

Joining Period:

Qualification:

If this role matches your profile and you’re available to join within 0–15 days, we’d love to hear from you!

Email:

📞 Contact:

Let’s connect and build something amazing together! 💡

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