Posted:19 hours ago|
Platform:
On-site
Full Time
Summary role description:
Hiring RTL Design Engineer for a global leader in electronic design and engineering solutions, empowering innovation in chips and advanced electronic systems.
Company description:
Our client is a global leader in providing design and engineering solutions, offering advanced tools that support engineers in creating and improving modern systems. The company is growing steadily and expanding into new areas, offering a dynamic environment where you can work on forward-looking projects and collaborate with a skilled global team.
Role details:
Role & responsibilities:
. Design and implement RTL for PCIe IP blocks while ensuring high-quality design through mandatory LINT, CDC, and synthesis checks.
. Define micro-architecture and design specifications in collaboration with system architects.
. Work closely with verification teams to build testbenches and validate the functionality of the design.
. Optimize the design for performance, power efficiency, and area across advanced technology nodes.
. Participate in PCIe interoperability testing to ensure compliance with protocol standards.
. Coordinate with cross-functional teams such as PHY, software, and validation for seamless integration.
Candidate requirements:
. 6+ years of strong hands-on experience in RTL design using Verilog/SystemVerilog, with deep expertise in PCIe protocol (Gen4/Gen5/Gen6).
. In-depth understanding of the PCIe protocol stack, transaction layers, and related controller subsystems. . Proficiency with AXI/PXC interfaces, DMA engines, and MSI-based interrupt handling. . Solid knowledge of CDC design principles, including asynchronous FIFO techniques. . Strong skills in synthesis, linting, and static timing analysis to ensure design quality and closure. . Experience with simulation tools, waveform debugging, and assertion-based or formal verification methods.
Selection Process:
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