RTL Design Engineer

We are seeking an experienced RTL Design Engineer to join our Digital Design team and contribute to the development of Aevas 4-D Lidar processing chip. The role involves implementing and integrating sub-components of the signal processing pipeline in ASICs and FPGAs, including filters, FFTs, and control logic. The engineer will be responsible for writing micro-architecture specifications, coding in SystemVerilog RTL, and validating Aeva-specific sub-components while ensuring functional safety, performance, and robustness.

Collaboration with architects, design engineers, verification teams, and system software engineers is essential to meet SOC-level performance, power, and functionality goals. The ideal candidate will have over 10 years of experience in DSP design and implementation, expertise in AMBA protocols, and strong RTL coding skills. Additional experience in LPDDR, Ethernet, MIPI, high-speed SerDes, FPGA validation, pre/post-silicon bring-up, and diagnostics firmware development is highly desirable. This position offers an opportunity to work on cutting-edge lidar signal processing technology in a high-performance environment.