Posted:9 hours ago|
Platform:
Work from Office
Full Time
We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team.
Key ResponsibilitiesWork closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPsCarry out floor planning, and physically aware synthesis on high-performance IPsPerform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL teamLeads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions and deliveriesResponsible for delivering the weekly status with desired metrics informationKey Technical SkillsSelf-starter with 312 years of relevant experience in synthesis, LEC, and constraints at the IP level. Candidate should be able to set up the synthesis and LEC flows from scratchStrong fundamentals of synthesis and place & route (P&R)Good scripting knowledge (TCL, Perl, Python)Knowledge of Fusion Compiler, Genus/Innovus, and Primetime
Mandatory Key Skills
TCL,Perl,Python,micro-management,Design Engineering,RTL.
Shashwath Solution
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