85 Power Analysis Jobs

Job description About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field.

Job description About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the AI SOC / CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the AI SOC/CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block. Qualifications Minimum Qualifications: Bachelor's with 13+ Years and Master's with 10+ Years of relevant experience in the semiconductor industry. 10+ years of experience in/withVerilog and system Verilog, synthesizable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 5+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug.

Job description About The Role Looking for enthusiastic, motivated and self-driven engineer in area of Power Analysis and Signoff who can take care of Understanding and Defining Chip Power & Performance Targets Analyzing FSDBs for various design power scenarios and extracting the right activity windows Running Power Estimation and Analysis at block level and roll-up total power for SoC Working with Architecture, Design and Implementation teams for power optimization Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out Qualifications BE/ME in Electrical Engineering with 8+ years of experience in Logic Design, Synthesis and Low Power Design/Implementation for complex multi-million gate SoCs Expertise in power analysis using PT-PX/Prime Power Experience in Verdi tool for FSDB analysis Experience in power analysis using Power Artist tool is a plus Experience in industry standard tools LP checks, PTPX for power estimation etc. Strong analytical and problem-solving skills Expertise in Tcl, Perl/Python is required Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Job description About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications Minimum Qualifications:BS+15 Years of relevant experience in the semiconductor I industry. experience15+ years of experience in/withVerilog and system verilog, synthesizeable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 10+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

As a Principal Product Engineer at Cadence, you will be a part of a team that is at the forefront of electronic design, leveraging over 30 years of computational software expertise to transform design concepts into reality. You will have the opportunity to work with the world's most innovative companies, contributing to the development of extraordinary electronic products across various dynamic market applications such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health sectors. Cadence offers a stimulating work environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the physical and mental well-being of our workforce, support career development, provide continuous learning opportunities, and recognize and celebrate individual and collective successes. Our unique "One Cadence - One Team" culture emphasizes collaboration both within and across teams to ensure customer success. In this role, you will work with a diverse and passionate team of individuals who are dedicated to exceeding customer expectations and making a difference every day. Cadence provides numerous avenues for personal and professional growth, regardless of where you are in your career journey. To excel in this position, you should have a solid understanding of Hardware Description Languages (HDL) such as Verilog, System Verilog, and VHDL, along with experience in logic synthesis tools. Proficiency in timing concepts, SDCs, PPA push and analysis, 1801/UPF concepts, awareness of P&R flows, and power analysis and optimization would be advantageous. The ideal candidate should hold a BE/BTech/ME/MS/MTech degree or equivalent qualification. If you are looking to be part of a team that is committed to solving challenging problems and making a meaningful impact, Cadence is the place for you. Join us in our mission to tackle what others cannot.,

Qualcomm India Private Limited is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 3+ years of Hardware Engineering experience, or a Master's degree with 2+ years of experience, or a PhD with 1+ year of experience. Key responsibilities include complete ownership of PNR implementation, including Floorplanning, Placement, CTS, post_route, etc., on the latest nodes. Signoff knowledge is mandatory, covering areas such as STA, Power analysis, FV, low power verification, PV, etc. The ideal candidate will possess hands-on experience with Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis, optimization, and signoff domains like LEC/CLP/PDN. Qualifications for this role include a minimum of 5 years of Hardware Engineering experience or related work experience, along with 5 years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm/10nm). A successful candidate should be a quick learner with strong analytical and problem-solving skills. Qualcomm is an equal opportunity employer committed to providing accessibility for individuals with disabilities during the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Please note that Qualcomm expects its employees to comply with all applicable policies and procedures, including security measures for protecting confidential information. Additionally, individuals seeking a job at Qualcomm should use the official Careers Site, as staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes. For further information about this role, please reach out to Qualcomm Careers.,

Job Overview As a part of in Arm&aposs Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM Designs. Analyze design timing, area and power to help improve the quality of ARM Design. Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams. Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results Required Skills And Experience Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification Strong Communication and Problem Solving Skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl, Python, Make. Nice To Have Skills And Experience Knowledge around Arm based SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary. Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [HIDDEN TEXT]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arms hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in PCIe IP design and development! We are looking for talented RTL Design Engineers to contribute to enhance and develop our IP. This is an incredible opportunity to be part of the PCIe and CXL development cycle, from specification to design. As an RTL Design Engineer, you will work in IP design and integration. You will be responsible for microarchitecture, RTL coding, create microarchitecture documents, Lint and Synthesis cycle and Timing closure. You will work with verification team on achieving test plan, the code & functional coverage. What You&aposll Do Deliver standards-compliant PCIe IP block. Will work on Micro-architect and document the design. Develop RTL design using Verilog and/or System Verilog. Work closely with the verification team in reviewing test suite/plans. Issue and track bug reports from launch to closure. Will refine IP development process with advancing tools/scripting. Work with our external customers or internal engineers to deliver designs for use. Collaborate with the team. You will be reporting to Principal Engineer of the Design team. What You&aposll Need B.E/M.Tech with 8+ years of experience in IP, ASIC or FPGA development. Knowledge and experience in any serial protocols and AMBA (AHB, AXI and CXS) protocol. Experience working on PCIe/CXL protocol is advantageous. Solid experience with Verilog, and System Verilog. Experience with FPGA development cycle is desirable. Experience with Lint, CDC, Synthesis, Timing closure, FPGA validation, Power analysis and LEC tools. Experience in ASIC tape-outs is a plus. Good experience with debugging tools and solid debugging skills. Experience with Unix/Linux Shell scripting and/or Perl, TCL, Python and C/C++ programming. Strong communication skills. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience - 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

KEY RESPONSIBILITIES: Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IPs Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Perform RTL Lint and work with the Designers. Analyze RTL CDC/RDC and work with Designer for potential Clock and Reset Design Domain crossing issues. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Implementing Functional ECOs using Conformal and writing manual Ecos. Work with Architects, RTL Designers and SOC teams for efficient IP Quality. PREFERRED EXPERIENCE: 5 to 10 years of experience inFront-end implementation from RTL to netlist Familiarity withPower Analysis Experience/Background on Computing/Graphics is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Senior Hardware Engineer Location: Hyderabad Age : 30+ years Experience : 5-10+ years Languages : English, Hindi and Telugu Qualification : Electronics Engineering Target Salary : 12 lacs Activities: Independent System Design and planning Independent board design, selection of parts Coordinate for design analysis reliability, thermal, signal integrity, power analysis, FMEA Coordinate with the program manager for providing inputs to project plan Review and track the projects periodically with concerned team members Prepare detailed work breakdown structure (WBS) and time schedule Review and track the projects periodically with concerned team members Interact with the customer to gather requirements, communicate the design, work status Manage project team hardware team members, mechanical team, software team members Skill Sets Understand product design from initial concept to manufacturing Should have worked in Processor based design, high speed board design, Microcontroller/FPGA Based Board Design, Analog and digital circuit design Good tool knowledge in minimum one EDA tool Part Selection, Schematics Drafting, Layout Review Should have worked in multi-layer board design, SI, PI and thermal analysis Knowledge of protocols UART, SPI, I2C, Wi-Fi, Ethernet, USB etc. Knowledge on memory device like DDR, Nor flash, eMMC Knowledge of Communication protocols (USB, Ethernet, MIL-STD-1553, ARINC-429, ARINC-717 etc.), interfaces with peripheral devices like memories, ADC etc. To provide guidance and technical assistance to Team Members Preparation of required design documentation Additional Skill Sets for FPGA Engineers In depth understanding of FPGA architecture and FPGA based design and verification flow. Strong knowledge in RTL(FPGA/SOC/IP) design architecture and coding experience in VHDL or Verilog Should have experience in FPGA board bring up and board level debugging of FPGA designs Should have worked on functional simulation timing simulations, etc. Analysis Timing Analysis, Signal Integrity Analysis and knowledge on high-speed digital design are added benefits.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

As a Hardware Architect at Kinara, a Bay Area-based venture backed company, you will play a crucial role in developing game-changing AI solutions that revolutionize what people and businesses can achieve. Your primary responsibility will be to develop architecture models for AI chips, ensuring that they accurately reflect design specifications and requirements. Collaborating with cross-functional teams, including hardware and software departments, you will work towards cohesive and efficient chip design and functionality. In addition to architecture modeling, you will conduct in-depth performance analysis to identify and resolve bottlenecks in AI chip designs. Using simulation and analytical methods, you will predict and enhance chip performance while working closely with software teams to validate performance models with real-world applications and workloads. Furthermore, you will perform detailed power analysis to ensure that AI chips meet stringent power consumption targets. To be successful in this role, you should hold a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with a minimum of 8 years of experience in hardware architecture/design of silicon chips. You must possess a strong understanding of computer architecture principles and AI chip design, as well as proficiency in C/C++/Verilog. Preferred qualifications for this position include excellent analytical and problem-solving skills, strong communication and teamwork abilities, the ability to work in a fast-paced, collaborative environment, and a detail-oriented approach with a focus on delivering high-quality results. At Kinara, we have an innovative environment that encourages technology experts to tackle exciting challenges while sharing responsibilities and valuing every point of view. If you are passionate about making a mark in the field of AI hardware architecture and are looking for a dynamic team to join, we look forward to reviewing your application. Join us at Kinara and be a part of creating a smarter, safer, and more enjoyable world through cutting-edge edge AI solutions.,

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

5+y in Physical design verification,Power analysis Tcl,AWK,python scripting Calibre,Innovus,Voltus layout edits in Innovus,power reports(IR, EM) from Voltus DRC report from Calibre fixing in Innovus IR,EM reports from Voltus fixing in Innovus

Design and develop integrated circuits, overseeing the definition, design, verification, and documentation for ASIC development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyze equipment to establish operation data, conduct experimental tests, and evaluate results. Also, review vendor capability to support development. Utilize wide-ranging experience and professional concepts to resolve complex issues creatively and effectively. Possess strong project management skills and lead the design and delivery of new products/processes. Demonstrate functional breadth and depth, as well as expertise in complementary fields. Apply broad concepts and theories to achieve innovative and effective solutions to complex problems. Work on complex issues requiring an in-depth evaluation of variable factors. Exercise judgment in selecting methods, techniques, and evaluation criteria for obtaining results. Network with key contacts outside own area of expertise. Champion significant projects, programs, and business initiatives using creativity and ingenuity. Lead major projects and influence or impact others" priorities, decisions, or activities. Serve as an escalation point for complex issues and coach and mentor other junior team members. Provide leadership for the work group through knowledge in the area of specialization. Determine work priorities based on general direction from managers. Determine methods and procedures on new assignments. Consult with management on long-range goals. Set own priorities, both tactical and strategic. Bachelor's degree and 8+ years of related experience; at this level post-graduate coursework may be desirable. Alternatively, a Master's degree and 6+ years of related experience or a PhD and 3+ years of related experience.,

Cadence Design Systems is seeking a Lead Hardware Engineer for their DFT IP R&D team in Noida with 4-6 years of experience. As a member of the R&D staff, you will be working on Cadence's MODUS DFT software solution, a comprehensive product designed to achieve high coverage, reduced test time, and superior PPA. We are looking for candidates with expertise in various areas such as RTL design, DFT architecture, verification, power analysis, and optimization. This role involves developing cutting-edge DFT tools, designing and verifying RTL and test benches, and providing support to application and product engineers. You will be part of a team responsible for creating innovative technologies in the DFT space. Your responsibilities will include designing, developing, and supporting the MODUS software product. This position offers an opportunity to build a solid foundation in logic circuits and contribute to DFT IP tool development. The role involves enhancing usability and quality through feature enhancement and rigorous verification. You will also provide R&D support, problem analysis, debugging, and develop new features to optimize synthesis results for timing, area, and power. At Cadence, we value innovation and research. The successful candidate will receive mentoring and support to contribute to the EDA problem domain and enhance their problem-solving skills. The ideal candidate should be proficient in RTL design using Verilog and SystemVerilog, have knowledge of front-end EDA tools, SystemVerilog assertions, and advanced verification techniques. Familiarity with scripting languages like Perl or Python, DFT methodologies, and synthesis tools is desirable. Excellent communication skills are essential, along with a strong foundation in data structures and algorithms. Qualifications for this position include an M.Tech, M.E, B.Tech, or B.E. in EE/ECE/CS or equivalent, a good understanding of Digital Electronics, prior knowledge of Verilog/System Verilog, and EDA tools. Join us at Cadence to work on projects that truly matter and help us solve challenges that others can't.,

As a Mechatronics Engineer in the Automotive industry based in Bangalore, you will be expected to possess a Bachelor's or advanced degree in Electrical/Electronics/Mechatronics Engineering with 2 to 6 years of relevant work experience. Your responsibilities will include working on electronic and electrical systems for automotive applications. You should have a strong background in circuit design and electronics circuit analysis, with the ability to identify optimization and failures in circuits. Your expertise should extend to automotive design and automotive EMC standards, along with a basic understanding of automotive EMC compliant PCB and circuit design. It is essential to have a clear understanding of technical datasheets of electronics components and the capability to design circuits according to the datasheet. Proficiency in electronic simulation tools such as Saber RD, LT Spice, ORCAD PSpice, or similar tools is required. Experience in Electronic design tools like Altium Designer or any other tool for circuit and PCB design is highly preferred. Additionally, familiarity with working on firmware for standard microcontrollers is expected. You will be responsible for hardware board design, debugging, and testing in the embedded hardware domain. Your role will involve designing high-speed digital boards according to requirements, schematic entry, PCB layout review, power analysis, DC analysis, power integrity, thermal analysis, board bring-up, testing, debugging, and capturing design documentations. Effective communication with team members and stakeholders is crucial for successful project execution. If you meet these requirements and are eager to contribute your skills to a dynamic automotive environment, we encourage you to apply for this position. Immediate to 30 days" notice period is preferred.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory* Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.