135 Power Analysis Jobs

As a DFT Verification Engineer, your role involves developing and executing pre-silicon verification test plans for DFT features of the chip. This includes verifying DFT design blocks and subsystems using complex SV or C++ verification environments. You will also be responsible for building test bench components, composing tests, assertions, checkers, and validation vectors to ensure verification completeness. Additionally, debugging regression test failures and addressing areas of concern to meet design quality objectives are key responsibilities. Key Responsibilities: - Develop and execute pre-silicon verification test plans for DFT features of the chip - Verify DFT design blocks and subsystems using complex SV or C++ verification environments - Build test bench components including agents, monitors, scoreboards for DUT - Compose tests, assertions, checkers, validation vectors, and coverage bins - Debug regression test failures and identify specification and implementation issues - Develop high coverage and cost-effective test patterns - Post silicon ATE and System level debug support of the test patterns delivered - Optimize test patterns to improve test quality and reduce test costs Qualifications Required: - 3 to 10 years of experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) - Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies, and C++ - Strong debug skills and experience with debug tools such as Verdi - Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi - Experience with scripting languages like Tcl/Perl/Ruby/Python - Working knowledge of Unix/Linux OS, file version control In addition to the preferred experience, having skills in ATE debug, Synthesis, formal/LEC, or power analysis would be a plus. Strong analytical/problem-solving skills, attention to detail, knowledge of STA Constraints for various DFT modes, and excellent written and verbal communication are essential for this role. Your educational background should include a minimum Engineering Degree in Electronics, Electrical, or Computer Science.,

Role Overview: As a highly skilled Post-Silicon Validation Engineer at our CPU design and validation team, you will be responsible for validating and verifying the functionality, performance, and reliability of CPU hardware after silicon fabrication. Your role will involve close collaboration with pre-silicon, firmware, software, and manufacturing teams to identify and debug silicon issues, improve test coverage, and ensure the CPU meets design specifications and quality standards. Key Responsibilities: - Develop and execute comprehensive post-silicon validation plans and test cases for CPU hardware. - Perform functional, performance, power, and reliability testing on silicon prototypes. - Collaborate with design, verification, firmware, and software teams to debug silicon issues using tools such as logic analyzers, oscilloscopes, JTAG, and embedded trace. - Analyze test failures, generate detailed bug reports, and drive issues to closure. - Develop automation scripts and tools to enhance test coverage and efficiency. - Validate CPU features including cores, caches, memory subsystems, interconnects, and power management. - Support bring-up and production ramp of silicon with manufacturing and yield teams. - Provide feedback to pre-silicon teams to improve design and verification quality. - Document test plans, methodologies, and validation results. - Stay current with CPU architecture, industry standards, and validation methodologies. Qualification Required: - Strong understanding of CPU microarchitecture and components (cores, caches, memory controllers, interconnects). - Experience with post-silicon validation methodologies and tools. - Proficiency in hardware debugging tools (logic analyzers, oscilloscopes, JTAG). - Strong scripting skills in Python, Perl, TCL, or similar languages. - Familiarity with embedded software/firmware and low-level software debugging. - Knowledge of performance and power analysis techniques. - Excellent problem-solving skills and attention to detail. - Strong written and verbal communication skills. Additional Company Details: The company focuses on Electrical, Electronics, and Semiconductor sectors. As a Post-Silicon Validation Engineer, you will develop competency in your area of expertise, share expertise with others, interpret clients" needs, work independently or with minimum supervision, identify and solve problems in straightforward situations, contribute to teamwork, and interact with customers.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a vital role in planning, designing, optimizing, verifying, and testing electronic systems that contribute to the launch of cutting-edge, world-class products. Your responsibilities will encompass working on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, Clock Tree Synthesis (CTS), post_route, etc. on latest nodes. - Mandatory signoff knowledge required in areas such as STA, Power analysis, low power verification, formal verification, etc. - Ability to quickly grasp new concepts with strong analytical and problem-solving skills. **Qualifications:** - Minimum of 20 years of Hardware Engineering experience or related work experience. - At least 17 years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm). If you are an individual with a disability and require accommodations during the application/hiring process, Qualcomm is dedicated to providing accessible support. You may contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number for assistance. Qualcomm values diversity and is an equal opportunity employer. Note: Qualcomm expects all employees to adhere to applicable policies and procedures, including security measures for protecting company confidential information. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. For more information about this role, please reach out to Qualcomm Careers directly.,

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

About The Role About The Role : We are looking for a Compute Validation Engineer with strong expertise in system debugging, embedded programming , and CPU architecture . The role involves working across pre-silicon and post-silicon phases, validating compute systems, and debugging using industry-standard tools. Key Responsibilities :Perform system-level debugging and validation across pre-silicon and post-silicon stages.Develop and test embedded software on bare-metal or embedded OS platforms.Work with JTAG debuggers and post-silicon debug tools.Analyze and validate CPU microarchitecture and coherent fabrics.Collaborate with hardware and software teams to ensure robust compute validation. Primary Skills : System Debugging (Pre-silicon & Post-silicon)Embedded OS / Bare Metal ProgrammingStrong C ProgrammingCPU Architecture KnowledgeJTAG DebuggersARM V8/V9 ArchitectureCPU Microarchitecture & Coherent Fabrics Secondary Skills (Good-to-Have): Experience with semiconductor validation flowsFamiliarity with performance and power analysis toolsExposure to SoC-level integration and testing About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

As an experienced Power Modeling and Estimation Engineer, you will be responsible for developing and driving a framework for highly optimized, modular, and scalable SoCs. Your primary focus will be on power analysis, power optimization, simulation, and roll-ups. You will utilize tools such as PTPX/Power artist and other industry-standard power estimation tools to achieve these objectives. Collaborating with various SoC and IP teams, you will work on power projections, requirements, silicon power capture, and correlation with pre-si estimates. Additionally, you will perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation. Minimum qualifications for this role include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field with over 10 years of relevant work experience in consumer electronics or semiconductor companies. You should have at least 5 years of experience in system design of small, medium, and large power management or power modeling systems, along with hands-on experience with PTPX/Power artist tools. Preferred qualifications include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field with 12+ years of relevant work experience. You should possess a strong ability to manage multiple projects, enhance the knowledge and capabilities of the power team, and conduct hands-on testing. A background in analog or digital power design would be advantageous. This is an Experienced Hire job type with Shift 1 (India) as the primary location. As part of The Client Computing Group (CCG), you will contribute to driving business strategy and product development for Intel's PC products and platforms. The goal is to deliver purposeful computing experiences that allow users to focus, create, and connect in ways that matter most to them. Please note that this role will be eligible for a hybrid work model, allowing you to split your time between working on-site at the assigned Intel site and off-site. Kindly be aware that job posting details, such as work model, location, or time type, are subject to change.,

We are seeking a highly skilled and motivated Power, Performance & Thermal (PPT) Engineer with 3-6 years of hands-on experience in analyzing and optimizing the power consumption, performance, and thermal characteristics of SoC/system platforms. The ideal candidate will have a strong background in DVFS (Dynamic Voltage and Frequency Scaling) and should be able to work across cross-functional teams to ensure efficient power and thermal management across hardware and software stacks. Key Responsibilities: Analyze and optimize power, performance, and thermal (PPT) behavior of SoCs and system platforms. Develop and implement DVFS strategies to improve energy efficiency across operating conditions. Work closely with hardware, software, and firmware teams to identify and resolve power and thermal issues. Perform system-level and component-level power profiling, thermal modeling , and performance analysis. Collaborate in defining power management architectures , algorithms, and controls. Develop automation scripts and tools to measure and monitor PPT metrics. Conduct regressions and benchmarking for various use-cases (idle, active, stress tests). Generate documentation and reports for internal stakeholders and customers. Required Skills and Experience: 3 to 6 years of relevant experience in Power, Performance, and Thermal engineering. Strong expertise in DVFS (Dynamic Voltage and Frequency Scaling) hands-on experience is a must . Proficiency in power and thermal modeling, measurement tools , and performance monitoring. Experience with Linux power management frameworks (cpufreq, devfreq, thermal zones, etc.). Good understanding of SoC architecture, clocking, voltage domains, and power rails. Scripting skills (Python, Shell, etc.) to develop automation tools for analysis and reporting. Experience with tools such as PowerAnalyzer, PTAnalyzer, or internal profiling tools. Familiarity with thermal mitigation techniques and power budgeting . Preferred Qualifications: Experience in mobile, embedded, or consumer electronic platforms. Knowledge of firmware and kernel-level power/thermal management. Exposure to Android Power HAL or Linux power drivers is a plus. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. What We Offer: Competitive salary up to 12 LPA Opportunity to work on cutting-edge SoC and system-level technologies Collaborative and innovative work environment Opportunities for learning and career growth

General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers onfloor-planning expertise at both block and top levelsfor industry-leadingCPU core designs, with a strong emphasis on scalability and achieving aggressivePower, Performance, and Area (PPA)targets. The role involves working oncutting-edge technology nodesand applyingadvanced physical design techniquesto push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Drivingfloorplan architecture and optimizationin collaboration with PD/RTL teams to maximize PPA Engaging incross-functional collaborationwith Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering withEDA tool vendorsand internal CAD teams to develop and enhanceautomation flows and methodologiesfor improved design efficiency Makingstrategic trade-offsin design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design less than 10nm Expect strong self-motivation and time management skills

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon NPU Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm - A Must

General Summary: Job Summary: We are seeking a highly motivated and skilled Performance and Power Analysis Engineer to join our Display Systems team in Bengaluru. In this critical role, you will be responsible for the analysis, modeling, and optimization of performance and power consumption across various stages of our cutting-edge chip development process. You will take the lead and collaborate closely with architecture, design, Software and verification teams to ensure our products meet stringent performance targets and power efficiency requirements. As an independent collaborator, contribute with cross functional teams, SoC performance and SW/HW teams to enhance or optimize the process. This is an exciting opportunity to contribute to the development of next-generation semiconductor technology. Responsibilities: Develop and maintain architectural-level and/or cycle-accurate models for performance and power estimation. Analyze trade-offs between performance, power, and area (PPA) at the architecture and microarchitecture levels. Drive performance and power analysis early in the design cycle to influence architecture and design decisions. Collaborate with architecture and design teams to explore and evaluate different design options and trade-offs to optimize performance and power. Conduct detailed analysis to identify performance bottlenecks and power inefficiencies in chip architectures and microarchitectures. Perform power profiling and characterization of designs under various operating conditions and workloads. Develop and implement power reduction techniques at different design stages (e.g., clock gating, power gating, voltage scaling). Analyze and debug performance and power-related issues during simulation, emulation, and silicon bring-up. Generate comprehensive reports and presentations summarizing analysis results and providing actionable recommendations to the design teams, cross-functional teams and senior leadership. Stay abreast of the latest industry trends, tools, and methodologies in performance and power analysis. Contribute to the development and improvement of internal tools and flows for performance and power analysis. Collaborate with verification teams to define and execute performance and power validation plans. Validate model accuracy through correlation with RTL simulations, emulation, and silicon measurements. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 8+ years of experience in performance and power analysis for ASIC or SoC designs. Strong understanding of computer architecture, microarchitecture, and digital design principles. Strong experience in developing and utilizing performance and power models using languages such as SystemC, Python, C++, or custom in-house frameworks. Proficiency in using industry-standard performance and power analysis tools (e.g., Synopsys PrimeTime PX) Solid understanding of power management techniques and low-power design methodologies. Experience with simulation and emulation environments. Strong analytical and problem-solving skills with the ability to interpret complex data and draw meaningful conclusions. Excellent communication and interpersonal skills with the ability to collaborate effectively with cross-functional teams. Familiarity with silicon bring-up and post-silicon power/performance characterization is a plus. Experience with machine learning techniques for power/performance prediction is a plus. Experience with IOS and Xcode profiling/development is a plus

General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. field. Minimum Qualifications: Good hands-onexperience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 20+ years Hardware Engineering experience or related work experience. 17+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams

The analyst will produce high-quality written content that communicates complex market dynamics clearly. Support insights with compelling visuals such as charts and graphs. The candidate will engage regularly with clients through calls, meetings, conferences, and events delivering tailored insights, explaining methodologies, and articulating value propositions. Responsibilities The analyst will conduct power modelling for power markets to deliver short-term market forecasts in client-facing reports. Key considerations in modelling may include, but are not limited to: Capacity build-up. Thermal fuel switching. Temperature-adjusted power demand. Power market mechanisms and price settlement methods. Carbon emission policy, cost, price and new technologies. Power and renewables policies, market trends and key players. Requirements A university degree in economics, business, public policy, or a related field. Familiarity with broader commodity markets, especially in the energy sector. Excellent English communication skills (reading/writing/speaking). Experience building forecasts or models. Knowledge of electricity markets in South and Southeast Asia. Experience with integrated cross-commodity analysis. Strong team players who can work across geographies and time zones. Proven ability to write clearly, visualize data effectively, and present complex analysis in high-level engagements and public forums. Having experience from a similar role is a plus.

General Summary: As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Job Overview Work with Qualcomm's security architecture / IP and access control team on next generation SOC for smartphone, tablet, automotive and IOT product categories. is responsible for assisting product development teams throughout the company to apply secure HW design principles to individual blocks, computing cores, and at the SoC level. SW/HW co-design, HW development experience. Familiarity with debug architectures such as JTAG and ARM coresight are a plus Successful candidates will be able to engage with product teams independently with minimal supervision to detect and mitigate security vulnerabilities in hardware architecture and implementations, involve in access control issues at both SW and HW. Minimum Qualifications 6 to 12 years of industry or academic experience in Security are required. Additionally, applicants must have expertise in two or more of the following areas: Computer architecture and hardware based or assisted access control and security Mobile platform security, Secure Boot, Secure Storage, Access Control, Secure Debug, DDR protection ARM TrustZone, Virtualization Operating system security and hypervisor security languages: C/C++, Python, RTL Teamwork across various teams and geolocations. Able to communicate in English, both verbal and written. Preferred Qualifications The following skills/experience will be considered a plus: ARM architecture SoC security design Applied Cryptography Trusted Computing Working Knowledge on hardware firewalls for access control Knowledge on AI/ML is added advantage SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design is a plus Side channel attacks, power analysis and timing attacks on crypto elements is a plus Memory technology (DDR4, DDR5), storage technologies is (eMMC, UFS) is a plus Educational Requirements: Required: Bachelor degree and above, Computer Engineering and/or Electrical Engineering Experience Requirements: Bachelors/ Masters with 5-7+ years Systems Engineering or related work experience

As a Principal Physical Design Engineer at our company, you will play a crucial role in leading a Physical Design team specializing in Low Power Design. Your responsibilities will encompass a wide range of tasks, from performing power analysis at different design stages to developing innovative power optimization techniques. You will be expected to lead and mentor a team, collaborate with cross-functional teams, manage external vendors, and stay updated on the latest advancements in the industry. Your expertise in RTL2GDSII design flow, power analysis and reduction using tools like PrimeTime PX/PrimePower, scripting languages such as TCL and Python, RTL design, and power optimization tools like Power-Artist will be essential. Additionally, your knowledge of low-power architecture, DVFS, memory sleep modes, UPF development, DFT considerations, and low-power verification will be highly valued. Desirable skills include proficiency in tools like FusionCompiler and/or Genus, automating processes using Make systems, Static Timing Analysis using Primetime, and knowledge of tools such as Mentor Calibre, Apache Redhawk, Tessent, Formality, and ICValidator. Strong project management capabilities, excellent communication skills, and the ability to solve complex problems are key attributes we are looking for. At our company, Sondrel, we foster a culture of innovation, collaboration, and personal growth. You will have the opportunity to work on challenging projects, drive technology advancements, and be part of a global team of highly skilled engineers. We offer competitive benefits, a supportive work environment, and opportunities for both domestic and international travel. If you are a proactive individual with a passion for continuous learning and enjoy working in a dynamic environment, we invite you to join our team at Sondrel and contribute to our mission of excellence in SoC design. We are an equal opportunities employer committed to creating an inclusive workplace where diverse perspectives are valued. Your growth and success are important to us, and we are dedicated to providing a fair and supportive environment for all our employees.,

As a Senior Digital IC Design Engineer at onsemi, you will be a part of the Digital Compute Team, contributing to the development of embedded MCU/DSP systems. Your responsibilities will include architecting, specifying, implementing, simulating, and benchmarking MCU and DSP systems, as well as hardware accelerators. You will collaborate with product integration teams, provide consultation during system integration, and participate in verification and FPGA prototyping activities. Additionally, you will lead project activities, coordinate SDK development with the software team, and contribute to design methodology and flow improvements. To excel in this role, you should possess a minimum BS/MS in Electrical Engineering or a related technical field, along with at least 5 years of relevant work experience in semiconductor product development, including engineering leadership. Proficiency in embedded CPUs such as ARM Cortex and DSP, as well as AMBA bus protocols like AHB/APB, is essential. You should have experience in RTL design of digital IP blocks and systems using Verilog/SystemVerilog. Strong technical document writing skills and excellent written and verbal communication skills in English are also required. Joining our team offers you the opportunity to work in a diverse and inclusive environment that fosters continual learning and growth. We provide a supportive atmosphere, competitive benefits package, and a platform for career advancement within a successful international company. By participating in interesting international projects, you can contribute to building a better future while enjoying a fulfilling work experience. If you are passionate about shaping a better future through innovative technologies and solutions, we invite you to join onsemi and define your future with us.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and Subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high performance and low power design techniques. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization. Own micro-architecture and implementation of IPs and subsystems. Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance and Area improvements for the domains owned.

About SiFive SiFive is at the forefront of introducing RISC-V to the global landscape, revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications worldwide. SiFive's unparalleled computing platforms are empowering leading technology firms across diverse market segments such as artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics to innovate and deliver cutting-edge solutions. With SiFive, the horizon of possibilities with RISC-V knows no bounds. At SiFive, we are enthusiastic about engaging with individuals who share our zeal for driving innovation and making a difference in the world. Our continuous innovation and sustained success stem from our exceptional teams of highly talented individuals who collaborate and support each other to conceive truly revolutionary ideas and solutions. These solutions are poised to significantly impact people's lives, contributing to making the world a better place, one processor at a time. Are you prepared for the challenge To delve deeper into SiFive's remarkable accomplishments and discover why we have been honored with the GSAs prestigious Most Respected Private Company Award (for the fourth consecutive time!), please explore our website and Glassdoor pages. Role: As a UPF power engineer at SiFive, you will collaborate with the Power Management Architect on feasibility studies. Your key responsibilities will include driving UPF methodology across frontend and backend teams for power intent and verification. Additionally, you will be tasked with supporting customers on UPF-related queries, collaborating with Platform engineering teams to devise scalable solutions for various design configurations. Responsibilities: - Drive UPF/CPF implementation, power/voltage domains, and power gating methodologies while working closely with the power management team. - Participate in low power design, drafting UPF, and verifying power intent at the chip level. - Engage in ASIC design flows and methodologies encompassing RTL, verification, synthesis, and static timing analysis (STA). - Collaborate with EDA vendors and tools team to establish new power methodologies, automate UPF generation, and conduct low power analysis. Required Skills: - Possess 2+ years of relevant experience. - Proficiency in Synopsys Verdi, Verdi UPF, and synthesis UPF. - Experience with power-aware simulations such as VCS/NLP or equivalent. - Familiarity with low power design implementation including UPF/CPF, multi-voltage domains, and power gating. - Knowledge of power intent definition, implementation, and verification flows. - Comprehensive understanding of ASIC design flows and IP design flows. - Strong scripting and programming skills in Python, Perl, or TCL languages. - Acquainted with power analysis and optimization methods. In this position, you will be required to undergo successful background and reference checks and provide satisfactory proof of your eligibility to work in India. Any offer of employment is subject to the Company's verification of your authorization for access to export-controlled technology under applicable export control laws or, when necessary, the successful acquisition of any essential export license(s) or approvals. SiFive is an equal opportunity employer. We value diversity and are dedicated to fostering an inclusive environment for all our employees.,

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping out high-performance microcontroller chips and collaborate with cross-functional teams including Chip team, Tech, and CAD. Developing scripts and methods for layout design automation will also be a part of your duties. Onsemi is dedicated to driving disruptive innovations in automotive and industrial markets to create a better future. The company focuses on megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a unique product portfolio, Onsemi develops intelligent power and sensing technologies to address complex global challenges and lead the way in building a safer, cleaner, and smarter world. Minimum qualifications for this role include a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience. Preferred candidates should have experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies. Proficiency in interpreting CALIBRE DRC, ERC, LVS reports, programming skills in SKILL, Perl, and/or Python, and experience with CADENCE or MENTOR GRAPHICS layout tools are desirable. Strong understanding of semiconductor manufacturing process, DFM techniques, and familiarity with Cadence Design Environment (CDE) and Unix OS are also required. Effective communication skills and a collaborative team spirit are essential for success in this role.,

Qualcomm India Private Limited is seeking an experienced Chipset Power System Engineer who is enthusiastic about tackling power challenges and developing innovative solutions to optimize power for the next generation Snapdragon chipsets across various platforms including applicator processor, modem, automotive, AR/XR, compute, and machine learning. As a Chipset Power System Engineer, you will collaborate with cross-functional engineering teams to model SOC/chipset power and devise creative solutions to enhance hardware and software for achieving world-class low power consumption in chipsets. Your responsibilities will include supporting existing tools and methodologies while shaping the long-term strategy in power modeling and methodology. You will be driving the engineering process to gather requirements, design, prioritize, and track tasks related to power, as well as test and deliver tools and methodologies to the power community. Additionally, you will maintain existing power modeling tools, define and provide API's as needed, create block-level and system-level power models, integrate power models from IP teams, and engage in cross-functional power modeling collaborations across hardware, systems, architecture, software, and post-silicon teams. Your role will also involve tracking technology advancements and enhancing power modeling methodologies with new low power techniques, algorithms, and power management schemes. In terms of power analysis, you will collaborate to evaluate use case power impact in various areas such as thermal and formfactor variance, architecture changes, IP changes, and low power techniques. You will also conduct block and chip-level power analysis and ensure that methodologies meet the requirements for these activities. Moreover, you will enable other teams to leverage the tools and methodologies for conducting technology-specific power analysis. To qualify for this position, you should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field with at least 2 years of Systems Engineering or related work experience. Alternatively, a Master's degree with 1+ year of experience or a PhD in a relevant field is also acceptable. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you require assistance due to a disability, you can contact Qualcomm at disability-accommodations@qualcomm.com. Please note that this email address is solely for requesting reasonable accommodations and not for application inquiries. Qualcomm expects its employees to comply with all applicable policies and procedures, including safeguarding Company confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is intended for individuals seeking employment directly with Qualcomm. Unsolicited applications from agencies will not be accepted. For further details about this role, please reach out to Qualcomm Careers for more information.,

You will be responsible for developing and driving the Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Your main tasks will include working on power analysis, power optimization, simulation, and roll-ups. You should have hands-on experience with PTPX/Power artist and other industry standard power estimation tools. Additionally, you will collaborate with various SoC and IP teams on power projections and requirements, including silicon power capture and correlation with pre-si estimates. Data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation will also be part of your responsibilities. Minimum qualifications for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 10 years of relevant work experience in consumer electronics or semiconductor companies. You should have a minimum of 5 years of experience with system design of small, medium, and large power management or power modeling systems, including hands-on experience with PTPX/Power artist tools. Preferred qualifications include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 12 years of relevant work experience. You should have a strong ability to manage multiple projects, grow knowledge and capabilities of the power team, and perform hands-on testing. A background in analog or digital power design would be advantageous. This role falls under the Experienced Hire job type and will be based in India, Bangalore. The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms. CCG aims to deliver purposeful computing experiences that unlock people's potential. As part of the largest business unit at Intel, CCG is investing heavily in the PC, ramping its capabilities more aggressively, and designing the PC experience more deliberately to deliver a predictable cadence of leadership products. By joining this team, you will have the opportunity to fuel innovation across Intel and help enrich the lives of every person on earth. Please note that the work model for this role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the Intel site and off-site. Kindly be aware that job posting details such as work model, location, or time type are subject to change.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC low power convergence and power analysis. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work closely with architecture, RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL and PD team for chip level power estimation, analysis and optimization Work closely with CAD team to come up with new flows and methodologies in the power analyisis and low power domains. PREFERRED SKILLSET: 8+ years of professional experience in the industry in low power and power estimation domains. Hands on experience on industry standard tools especially PTPX, Power Artitst, VCLP and CLP. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Qualcomm India Private Limited is a leading technology innovator that enables next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience. - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. Additional Job Description: You will have complete ownership of PNR implementation for Qualcomm SoC's, with hands-on experience in Floorplanning, PNR, and STA flows. Good knowledge in Placement/Clock Tree Synthesis (CTS), optimization, and signoff domains such as LEC/CLP/PDN is required. Familiarity with Unix/Linux, Perl/TCL fundamentals/scripting is essential. Principal Duties and Responsibilities: - Take ownership of PNR implementation including Floorplanning, Placement, CTS, post_route, etc. - Mandatory signoff knowledge in areas such as STA, Power analysis, FV, low power verification, PV, etc. - Quick learner with strong analytical and problem-solving skills. Qualifications: - 5+ years of Hardware Engineering experience or related work experience. - 5+ years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm/10nm). Qualcomm is an equal opportunity employer that provides accommodations for individuals with disabilities during the application/hiring process. For accommodation requests, you may contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. The company expects employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm, and staffing/recruiting agencies are not authorized to use this site. Unsolicited resumes or applications from agencies will not be accepted. For more information about this role, please reach out to Qualcomm Careers.,