About the job ASIC/SoC/FPGA Design Verification (Bangalore, Chennai and Hyderabad) Design Verification with planning, architecture, development, maintenance, and execution on complex IPs and/or SOCs. Strong knowledge of digital design principles and computer architecture. Proficiency in verification languages like Verilog or SystemVerilog. Experience with UVM (Universal Verification Methodology).

Should have around 6+ years of working experience in SAP ISU as a Techno-functional / functional expert, experience in S/4 Hana for utilities is preferred Expertise in ISU development in areas like Billing, device management or FICA Experience of working as Techno- functional lead in at-least 1 end to end SAP for utilities implementations Should have worked in at-least one S/4 HANA implementation as a consultant in customer facing role Excellent interpersonal and communication skills Well versed Architecture and solution nuances of S/4 HANA with good knowledge on SAPs road map Location Bangalore/Hyderabad/Pune/Chennai

Your Role and Responsibilities As a Logic Design Engineer, you will play a pivotal role in the end-to-end development of features with significant impact on our Mainframe and/or Power customers. From conceptualization to validation, you will be responsible for developing features, presenting proposed architectures, estimating efforts, and collaborating across various teams to ensure successful implementation. Your primary responsibilities include: Feature Development and Architecture: Develop features and propose architectures in high- level design discussions, ensuring alignment with project goals and customer requirements. Effort Estimation: Estimate the overall effort required for feature development, providing valuable input to project planning and scheduling. Cross-Functional Collaboration: Collaborate with verification, physical design, test generation, and mill code teams to develop features, fostering cross-functional teamwork and synergy. Pre-Silicon Design Sign-off: Sign off on design during the pre-silicon phase, ensuring eadiness for tape-out and fabrication. Post-Silicon Validation: Validate hardware functionality post-silicon, conducting thorough testing to ensure feature integrity and performance. Required Technical and Professional Expertise Microarchitecture and Logic Design: 3 to 8 years of experience in microarchitecture and logic design, demonstrating proficiency in designing complex digital systems. VLSI Design in VHDL/Verilog: Experience with VLSI design using hardware description languages such as VHDL or Verilog, enabling efficient implementation of digital logic. Processor Architecture Understanding: Good understanding of processor architectures, including RISC and CISC, facilitating the development of features tailored to specific processor requirements. Designer Simulations: Experience in developing and performing designer simulations, ensuring functionality and performance goals are met prior to silicon realization. Design Closure and Verification Coverage: Proven ability to drive design closure, including test plan reviews and verification coverage analysis, ensuring comprehensive validation of designs. Preferred Technical and Professional Experience Power-Efficient Logic Design: Experience in designing power-efficient logic, optimizing designs for low power consumption without sacrificing performance. Physical Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical implementation and timing closure processes. Python Scripting: Proficiency in Python scripting, enabling automation of design tasks and enhancing productivity in design workflows.

You are best equipped for this task if you have: Should have experience of 5 years Strong Low Power Concepts including UPF IEEE format and constructs. Debug skills required on Synthesis run issues like : RTL not synthesizable, UPF, constraints related impact on Synthesis, Logical Equivalence Checking , Abort resolutions and Non Equivalence Debugging skills. Good to have Physical aware synthesis knowledge , LEF/DEF formats, basics of synthesis should be strong.

Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration

Full-Time Role Overview We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test- cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans. ability to interface with different teams and prioritize work based on project needs.

Skills Required 10-15years of relevant experience in ASIC Physical Verification Good understanding of overall design Flow from RTL to GDS. Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Siemens Tools Good knowledge on PnR flow Knowledge on Perl / TCL / Python scripting language Experience on multi voltage designs Good understanding of all Phases of Physical Design (PnR/STA/PV/IR) Responsibilities Responsible for Block/ Chip Tile PV closure to achieve the best PPA DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 5nm/3nm nodes Interaction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving Conflicts Able to work on multiple blocks at same time with minimal supervision Responsible for Full Chip LVS & DRC closure Responsible for Analog integration closure for all IP"s used in SOC Interactions with Foundry team for Full chip Tapeout

Responsibilities Design and maintain standard cells for new products based on new technology. Characterize the performance of standard cells and optimize the standard cell design and layout. Characterization and modeling of Standard Cell and semi-Custom cells to provide timing/power model for verification. Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality. Closely collaborate with DTCO team to work on stdcells architecture for emerging technologies. Develop automation test bench/flow/tools to improve the work efficiency and help data analysis. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics, ICC flow is added an advantage. Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design and verification Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis is a plus Previous work experience in DRAM memory related fields or analog blocks is a plus. Must possess good interpersonal & communication skills and ability to work well in a team

Required Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field with 15 years or more relevant experience. Experience with use-case analysis and decomposition. Experience in Linux, Zephyr, Free RTOS or similar operating systems. Strong understanding of microprocessor and micro controller architectures, including CPU cores , DSP, memory management, and peripheral integration. Experience with system level performance optimization, low-power design, SW/HW co-design , and real-time processing. Familiarity with high-speed interconnects, memory architectures, DDR, PCIe, and bus protocols. Strong collaboration skills to work across multidisciplinary teams, including silicon, software, hardware, board design, and validation engineers. Experience in product development processes. Preferred Qualifications: Experience with ARM Cortex and/or RISC-V architecture. Experience with media processing, vision and imaging applications. Experience with system-level simulation tools, hardware/software co-design, and debugging techniques. Familiarity with Machine Learning Hardware IPs, tools, and architecture. Knowledge of functional safety and security standards. Familiarity with Wi-Fi integration, networking protocols, and secure wireless communication.

IO Design Work Location: Bangalore Experience: 5 to 15+ years In your new role you will: Technically Lead complete design & development of IO library Lead interaction with system architects of product development to close IO specifications & requirements. Drive IO integration into sub-system resolving all technical issues. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system. Own IO quality sign-off & checklist at different milestones to ensure quality deliverables to SOC. Drive the definition of the overall concept(circuit/layout) including the sub-blocks in alignment with product requirements. Guide the team members on the effective implementation of the IOs. Review their designs and continuously drive the turnaround time, design robustness/optimizations and area/power of IOs Review their designs and continuously drive the turnaround time, design robustness/optimizations and area/power of IOs Support the design development hands-on as per the project needs. Continuous improvement and development of design and verification methodologies for improving quality and efficiency. Ensuring compliance with all Quality/Process practices for library development. You are best equipped for this task if you have: Solid experience in IO design, preferable for interface standards like LVTTL, LVCMOS, DDR, SPI, xSPI , Oscillator, LVDS , over voltage/under voltage tolerant circuits . Good understanding of ESD & LU concepts. Good understanding of the characterization methodology used in the IO library development. Candidate should be able to technically lead a team of designers/layout engineers and come up with new architectures and plan schedules. Candidate should have delivered few designs from spec to silicon with solid knowledge of associated deliverables and the development flow. Disciplined process management, problem solving skills, multi tasking ability and attention to quality and detail. Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different function