You should possess a Bachelors/Master's degree in Computer Science/Computer Engineering or a related field. Along with this, you must have at least 2-6 years of experience in server-side development using languages like GoLang, Node.JS, or Python. Furthermore, it is essential to have proficiency in AWS services such as Lambda, DynamoDB, Step Functions, S3, etc. and hands-on experience in deploying and managing Serverless service environments. Experience with Docker, containerization, and Kubernetes is also required for this role. In addition, knowledge of database technologies like MongoDB and DynamoDB, along with experience in CI/CD pipeline and automation, would be beneficial. Experience in Video Transcoding/Streaming on Cloud would be considered a plus. Lastly, strong problem-solving skills are a must-have for this position.,
The ideal candidate for this position should have a Bachelor's or Master's degree in Computer Science or Computer Engineering, or an equivalent field. You should possess at least 2-6 years of experience in server side development using technologies such as GoLang, Node.JS, or Python. You should demonstrate proficiency in working with AWS services like Lambda, DynamoDB, Step Functions, and S3. Additionally, you should have hands-on experience in deploying and managing Serverless service environments. Experience with Docker, containerization, and Kubernetes is also required for this role. A strong background in database technologies including MongoDB and DynamoDB is preferred. You should also have experience with CI/CD pipelines and automation processes. Any experience in Video Transcoding / Streaming on Cloud would be considered a plus. Problem-solving skills are essential for this role as you may encounter various challenges while working on projects.,
The role involves layout design of memory circuit/digital design on the latest technology nodes. As an Engineer, you are expected to have a good attitude, seek new challenges, possess good analytical and communication skills. You should have the ability and desire to learn quickly and excel as a team player. Your key responsibilities will include implementing the layout of digital circuits, conducting DRC, LVS, and other physical verification checks, designing floor-plans, routing, addressing crosstalk fixes, electro-migration fixes, and IR fixes. You will also be handling different tools such as Calibre and Virtuoso. Preferred experience for this role includes a strong background with tools for schematics and layout, proficiency in scripting languages to automate layout flow, excellent communication skills, ability to multitask across projects, collaborate with geographically spread-out teams, experience in FinFET & Dual Patterning nodes like 16/7/5/3nm, a good understanding of CMOS basics and digital circuits, strong analytical and problem-solving skills with attention to detail. To qualify for this position, you should hold a Bachelor's degree in Electronics/Electrical Engineering and possess skills in electro-migration fixes, design rule checking (DRC), physical verification checks, layout design, scripting languages, LVS, Calibre, crosstalk fixes, routing, IR fixes, Virtuoso, skill scripts, floor-plan design, and digital design.,
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications. Experience 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification. Solid Experience on SV UVM Hands-on experience with power-aware simulation and verification tools. Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS). Proficiency in low-power UPF/CPF-based verification Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor). Preferred Qualifications Experience with scripting languages like Python, Perl, or TCL for automation. Knowledge of power estimation and optimization techniques. Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications) Skills: tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis
Job Position - Emulation Engineer Overview - Experienced in emulation platforms (Palladium, Veloce, Zebu), Verilog, VHDL, C/C++, and System Verilog. Skilled in scripting (Perl, Python, Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE, USB, DDR, and SPI. Strong communication skills and team collaboration. Holds a Bachelor’s degree with 5+ years of industry experience. Experience Required: Minimum 4 years relevant experience is required. Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience. Skills: system verilog,emulation platforms (palladium, veloce, zebu),waveform debug (verdi/simvision),protocols (pcie, usb, ddr, spi),verilog,python,perl,c/c++,simvision,emulation,vhdl,scripting (perl, python, makefile)
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications. Experience 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification. Solid Experience on SV UVM Hands-on experience with power-aware simulation and verification tools. Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS). Proficiency in low-power UPF/CPF-based verification Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor). Preferred Qualifications Experience with scripting languages like Python, Perl, or TCL for automation. Knowledge of power estimation and optimization techniques. Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications) Skills: tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis
Job Position - Emulation Engineer Overview - Experienced in emulation platforms (Palladium, Veloce, Zebu), Verilog, VHDL, C/C++, and System Verilog. Skilled in scripting (Perl, Python, Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE, USB, DDR, and SPI. Strong communication skills and team collaboration. Holds a Bachelor’s degree with 5+ years of industry experience. Experience Required: Minimum 4 years relevant experience is required. Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience. Skills: system verilog,emulation platforms (palladium, veloce, zebu),waveform debug (verdi/simvision),protocols (pcie, usb, ddr, spi),verilog,python,perl,c/c++,simvision,emulation,vhdl,scripting (perl, python, makefile)
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications. Experience 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification. Solid Experience on SV UVM Hands-on experience with power-aware simulation and verification tools. Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS). Proficiency in low-power UPF/CPF-based verification Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor). Preferred Qualifications Experience with scripting languages like Python, Perl, or TCL for automation. Knowledge of power estimation and optimization techniques. Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications) Skills: tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis
Job Position - Emulation Engineer Overview - Experienced in emulation platforms (Palladium, Veloce, Zebu), Verilog, VHDL, C/C++, and System Verilog. Skilled in scripting (Perl, Python, Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE, USB, DDR, and SPI. Strong communication skills and team collaboration. Holds a Bachelor’s degree with 5+ years of industry experience. Experience Required: Minimum 4 years relevant experience is required. Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience. Skills: system verilog,emulation platforms (palladium, veloce, zebu),waveform debug (verdi/simvision),protocols (pcie, usb, ddr, spi),verilog,python,perl,c/c++,simvision,emulation,vhdl,scripting (perl, python, makefile)
Key Responsiblities Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. Preferred Skillset 3+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker Academic Credentials Bachelors or Masters degree in Electronics/Electrical Engineering Skills: perl,tcl,soc,power delivery,power integrity,full chip,power delivery design.,cad,redhawk
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications. Experience 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification. Solid Experience on SV UVM Hands-on experience with power-aware simulation and verification tools. Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS). Proficiency in low-power UPF/CPF-based verification Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor). Preferred Qualifications Experience with scripting languages like Python, Perl, or TCL for automation. Knowledge of power estimation and optimization techniques. Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications) Skills: tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis
Job Position - Emulation Engineer Overview - Experienced in emulation platforms (Palladium, Veloce, Zebu), Verilog, VHDL, C/C++, and System Verilog. Skilled in scripting (Perl, Python, Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE, USB, DDR, and SPI. Strong communication skills and team collaboration. Holds a Bachelor’s degree with 5+ years of industry experience. Experience Required: Minimum 4 years relevant experience is required. Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience. Skills: system verilog,emulation platforms (palladium, veloce, zebu),waveform debug (verdi/simvision),protocols (pcie, usb, ddr, spi),verilog,python,perl,c/c++,simvision,emulation,vhdl,scripting (perl, python, makefile)
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications. Experience 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification. Solid Experience on SV UVM Hands-on experience with power-aware simulation and verification tools. Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS). Proficiency in low-power UPF/CPF-based verification Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor). Preferred Qualifications Experience with scripting languages like Python, Perl, or TCL for automation. Knowledge of power estimation and optimization techniques. Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications) Skills: tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis
Job Position - Emulation Engineer Overview - Experienced in emulation platforms (Palladium, Veloce, Zebu), Verilog, VHDL, C/C++, and System Verilog. Skilled in scripting (Perl, Python, Makefile) and waveform debug (Verdi/SimVision). Familiar with protocols like PCIE, USB, DDR, and SPI. Strong communication skills and team collaboration. Holds a Bachelor’s degree with 5+ years of industry experience. Experience Required: Minimum 4 years relevant experience is required. Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience. Skills: system verilog,emulation platforms (palladium, veloce, zebu),waveform debug (verdi/simvision),protocols (pcie, usb, ddr, spi),verilog,python,perl,c/c++,simvision,emulation,vhdl,scripting (perl, python, makefile)
As a Senior Recruiter for Semiconductor, your role is crucial in attracting and securing top talent within the semiconductor industry. Your collaboration with hiring managers to understand staffing needs and develop effective recruitment strategies will drive the organization's growth and success. Leveraging industry contacts, social media, and recruitment tools, you will identify high-caliber candidates and enhance the employer brand to attract skilled professionals. Furthermore, your responsibilities include optimizing the recruitment process through data-driven insights to improve the candidate experience and streamline hiring outcomes. Your passion for building a diverse talent pool and understanding of the semiconductor landscape will ensure the organization is well-positioned to meet its talent needs in a rapidly evolving industry. Key Responsibilities: - Partner with hiring managers to define staffing needs. - Develop and implement creatively targeted recruitment strategies. - Source candidates through various channels, including social media and industry events. - Conduct thorough candidate assessments and interviews. - Maintain relationships with potential candidates for future openings. - Build a strong employer brand in the semiconductor sector. - Utilize data analytics to enhance hiring processes and reduce time-to-fill. - Provide regular updates and reports on recruitment metrics to stakeholders. - Participate in job fairs and industry networking events. - Guide hiring managers in crafting compelling job descriptions. - Manage the offer process, ensuring competitive and fair compensation. - Foster a diverse applicant pool through targeted outreach. - Support onboarding efforts for new hires to ensure a smooth transition. - Monitor industry trends to inform recruitment strategies. - Continuously seek feedback to improve recruitment practices. Qualifications Required: - Bachelor's degree in Human Resources, Business, or a related field. - 3+ years of experience in recruiting, specifically in the semiconductor or technology fields. - Proven track record of successful talent acquisition. - In-depth understanding of semiconductor industry roles and skills. - Strong familiarity with applicant tracking systems (ATS) and recruitment tools. - Excellent interpersonal and communication skills. - Solid analytical skills and ability to leverage data for decision making. - Experience in employer branding and strategic recruitment. - Ability to work independently and manage multiple roles simultaneously. - Familiarity with labor laws and ethical recruiting practices. - Strong negotiation skills regarding offers and candidate expectations. - Proficiency in the use of social media and networking platforms for recruitment. - Ability to build and maintain strategic relationships within the industry. - Commitment to diversity and inclusion in hiring practices. - Willingness to travel to attend events and conduct in-person interviews as needed. In this role, you will play a key part in shaping the organization's talent acquisition strategy and ensuring the attraction of top talent in the competitive semiconductor industry. Your expertise in recruitment, knowledge of the semiconductor landscape, and commitment to diversity and inclusion will be instrumental in driving success.,
No. of Positions: 3 Location: Hyderabad, India Experience Required: 5+ years of relevant experience We are seeking highly skilled and motivated C++ Developers to join our engineering team in Hyderabad. The ideal candidate will bring deep technical expertise in C++, along with proficiency in Python and a strong understanding of computer architecture and system-level programming. This position offers an opportunity to work on complex, high-performance systems, optimizing software for speed, scalability, and reliability. As part of our core development team, you will play a critical role in designing, developing, and maintaining performance-driven applications, with the chance to collaborate across hardware and software teams. You will be expected to analyze, design, and implement features that push the limits of computing performance, especially in environments where multithreading, memory optimization, and low-level system interaction are essential. Key Responsibilities Software Development: Design, develop, and maintain high-performance C++ applications for complex system-level and computational tasks. Write efficient, optimized, and clean code that adheres to best coding practices and design patterns. Participate in full software development lifecycle, including requirement analysis, design, implementation, integration, testing, and deployment. System Optimization and Debugging: Perform in-depth code profiling, debugging, and performance optimization at both software and hardware levels. Utilize strong analytical and debugging skills to troubleshoot issues and ensure stability, scalability, and performance of the developed modules. Collaborate with system and hardware teams to fine-tune software for optimal performance across various architectures. Collaboration and Cross-Functional Integration: Work closely with cross-functional teams including architects, QA engineers, and research scientists to ensure robust and scalable implementations. Contribute to code reviews, architectural discussions, and performance evaluations. Document development processes, algorithms, and design decisions to ensure transparency and maintainability. AI/ML and GPU Integration: Leverage foundational understanding of AI/ML concepts to integrate computational algorithms and optimize workflows for intelligent data processing. Collaborate with AI and GPU engineering teams to accelerate computations using GPU-based architectures. Optimize data flow and computation for multicore and GPU systems to achieve maximum efficiency. Required Skills And Qualifications Technical Expertise: Minimum of 5 years of hands-on experience in C++ software development, with proven contributions to performance-critical applications. Strong proficiency in C++11/14/17 or later, including templates, STL, and memory management techniques. Good working knowledge of Python for automation, scripting, or prototyping purposes. Experience in assembly-level coding and optimization for performance tuning. Solid understanding of computer architecture, CPU pipelines, caches, and memory organization. Working knowledge of multithreading, synchronization primitives, and multicore optimization strategies. Excellent debugging and profiling skills, including use of performance analysis tools and debuggers. Preferred Skills: Exposure to GPU architectures such as CUDA or OpenCL, and understanding of parallel processing paradigms. Familiarity with AI/ML concepts and frameworks for integrating intelligent algorithms into performance-driven applications. Experience in low-latency system design or real-time application development is a plus. Working experience with version control systems such as Git, and CI/CD pipelines. Soft Skills: Strong analytical, problem-solving, and critical-thinking abilities. Self-motivated with a passion for system-level programming and continuous learning. Effective communication and teamwork skills, with the ability to collaborate in an agile development environment. Detail-oriented mindset with a focus on quality, performance, and reliability. Skills: assemble level coding,multithreading,multicore,c++
Job Description B.Tech or M.Tech in Computerss/Electronics/Electrical Engineering with minimum of 4 years of strong, hands on block/sub HM level Timing closure or chip top level timing closure. Should have experience in 28nm below technologies experience in 10nm below is an added advantage Should be open to work from Hyderabad or Bangalore. Skills Required Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Scripting experience in Perl/TCL. Excellent debugging skills in implementation issues and ability to come up with creative solutions . Technologies from 28nm and below. Skills: scripting experience in perl/tcl,sta,timing,prime,timing closure at sub hm/block/top level,excellent debugging skills,netlist and constraint sign in checks and validation,top level timing closure with sign off sta in mmmc,prime time constraint development,multimode multi corner timing knowledge,xtalk and ocv,eco implementation strategy development for netlist, rtl and timing level changes,timing closure
As an experienced professional with 3-5 years of experience in the field, your role will involve understanding low power design features and optimization techniques. This includes familiarity with static and dynamic power saving schemes encompassing architecture, design, and power management. You should be able to effectively balance trade-offs between power, performance, and area. Additionally, your proficiency in Verilog or System Verilog along with fundamental RTL design skills will be crucial for this role. Experience with tools such as PrimePower, PowerArtist, and PP-RTL for power analysis, power delivery, and signoff will be highly beneficial. Knowledge of the ASIC Physical Design flow from RTL through Synthesis, Place & Route is also required. Key Responsibilities: - Understanding low power design features and optimization techniques - Balancing trade-offs between power, performance, and area - Proficiency in Verilog or System Verilog and fundamental RTL design skills - Experience using tools for power analysis, power delivery, and signoff (e.g. PrimePower, PowerArtist, PP-RTL) - Knowledge of ASIC Physical Design flow from RTL through Synthesis, Place & Route Qualifications Required: - 3-5 years of experience in the field - Proficiency in Verilog or System Verilog - Familiarity with ASIC Physical Design flow - Experience with power analysis tools - Strong understanding of low power design features In addition to the above qualifications, it would be beneficial to have a background in running simulation and emulation tools such as VCS, Palladium, and Zebu. Knowledge around graphics benchmarks and workload analysis would also be considered a plus. Please note that the location for this position is in Bangalore.,
Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 3+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of PCIe and CXL protocols is an added advantage Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI Comments For Suppliers Skills: design verification,universal verification methodology (uvm),system verilog
Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 3+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of PCIe and CXL protocols is an added advantage Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI Comments For Suppliers Skills: design verification,universal verification methodology (uvm),system verilog