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SOC DFT Lead/Manager Intel

8.0 - 15.0 years

0 Lacs

karnataka

On-site

Role Overview: You will be part of the Client Development Group (CDG) as a Design for Test engineer, responsible for developing logic design, RTL coding, simulation, DFT timing closure support, test content generation, and delivery to manufacturing for various DFx content. Your role will involve participating in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. You will apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Additionally, you will optimize logic to qualify the design for power, performance, area, timing, and design integrity for physical implementation....

Posted 1 month ago

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