Physical Design - SOC / GPU

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA). - Utilize industry standard tools like ICC, DC, PT, VSLP, Redhawk, Calibre, Formality, and be able to leverage their capabilities. - Have proficiency in scripting languages such as Perl and Tcl, and implementation flows. - Work on large SOC designs (>20M gates) with frequencies over 1GHz. - Expertise in block-level and full-chip SDC clean up, Synthesis optimization, Low Power checking, and logic equivalence checking. - Familiarity with deep sub-micron designs (8nm/5nm) and related issues like manufacturability, power, signal integrity, and scaling. - Understand typical SOC issues including multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. - Skilled in hierarchical design, top-down design, budgeting, timing, and physical convergence. - Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. - Have experience with recent successful SOC tape-outs. Qualifications Required: - Bachelor's or Master's degree in Electrical Engineering or related field. - Minimum of X years of experience in physical design and timing closure. - Proficient in using industry standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality. - Strong understanding of scripting languages like Perl and Tcl. - Experience with large SOC designs and frequencies exceeding 1GHz. - Knowledge of deep sub-micron designs (8nm/5nm) and associated challenges. - Familiarity with hierarchical design, top-down design, and physical convergence. - Good understanding of Physical Design Verification methodology. - Experience with recent successful SOC tape-outs would be a plus.,