8.0 - 12.0 years

0 Lacs

noida, uttar pradesh

On-site

As a Design Engineer - II at TekWissen Group in Noida, you will be responsible for hardware board design in a customer-centric information technology environment. You should possess a Bachelor's degree in electronics, product & industrial design, or a related field, with a Master's degree considered a plus. With a minimum of 8+ years of experience in hardware board design or a similar manufacturing environment, you are expected to have a solid understanding of the manufacturing process, quality requirements, and DFM process. Your role will require expertise in high-speed digital signal design and testing, as well as a thorough understanding of electronics components. Proficiency in Cadence tools, including Allegro and OrCAD, and experience with Hierarchical design are essential. You should have strong technical and analytical skills to troubleshoot and debug electronic systems effectively. Experience with NXP processors, DDR4, Power designs, and RF designs is necessary for this position. Excellent interpersonal and communication skills, teamwork adaptability, and proficiency in oral and written English are highly valued. As an equal opportunity employer, TekWissen Group supports workforce diversity to foster an inclusive work environment.,

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Physical Design - SOC / GPU Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer, you will be responsible for the complex SOC top physical implementation of next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of both complex blocks and full-chip designs. You will be expected to demonstrate expertise in top-level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. A strong understanding of timing, power, and area trade-offs, as well as optimization of PPA, will be crucial for success in this role. The ideal candidate will be a power user of industry-standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality, and should be able to leverage their capabilities effectively. Proficiency in scripting languages like Perl and Tcl, along with a deep understanding of implementation flows, will be essential. Experience with large SOC designs exceeding 20M gates and operating at frequencies above 1GHz is highly desirable. You should possess expertise in block-level and full-chip SDC clean up, Synthesis optimization, Low Power checking, and logic equivalence checking. Familiarity with deep sub-micron designs, particularly at 8nm and 5nm nodes, and associated challenges related to manufacturability, power, signal integrity, and scaling, will be advantageous. Understanding typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions is also important. You should be well-versed in hierarchical design, top-down design, budgeting, timing, and physical convergence. A good understanding of Physical Design Verification methodology to debug LVS/DRC issues at both chip and block levels is expected. Ideal candidates will have participated in recent successful SOC tape-outs, showcasing their ability to deliver high-quality designs.,

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Physical Design with Innovus Magnus Hr Consulting

7.0 - 12.0 years

32 - 47 Lacs

Bengaluru

Work from Office

Experience place & route flow, hierarchical design,Synthesis, Static Timing Analysis ,7nm, hierarchical designs

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