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5.0 - 9.0 years
0 Lacs
karnataka
On-site
Role Overview: You will be responsible for the complex SOC Top Physical Implementation of next generation SOCs, including mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing and physical signoffs. Additionally, you will work on physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Perform top level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs for optimization of PPA. - Utilize industry standard ...
Posted 1 week ago
5.0 - 7.0 years
0 Lacs
noida, uttar pradesh, india
On-site
#Urgent_Opening_for_Canvendor #Hiring: PD Floor Plan Engineer (5+ years) | Noida| Immediate Joiners Preferred Location: Noida, India Experience: 5+ years Notice period: Immediate #Key_Requirements: Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII. Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans. Perform macro placement , power grid planning , pin placement , and block-level partitioning . Analyze and optimize for congestion , timing , area , and power . Work closely with place & route , clock tree synthesis , and timing closure teams to ensure floorplan quality. Required Skills: Strong ha...
Posted 2 weeks ago
5.0 - 9.0 years
0 Lacs
karnataka
On-site
Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....
Posted 2 months ago
8.0 - 12.0 years
0 Lacs
noida, uttar pradesh
On-site
As a Design Engineer - II at TekWissen Group in Noida, you will be responsible for hardware board design in a customer-centric information technology environment. You should possess a Bachelor's degree in electronics, product & industrial design, or a related field, with a Master's degree considered a plus. With a minimum of 8+ years of experience in hardware board design or a similar manufacturing environment, you are expected to have a solid understanding of the manufacturing process, quality requirements, and DFM process. Your role will require expertise in high-speed digital signal design and testing, as well as a thorough understanding of electronics components. Proficiency in Cadence t...
Posted 4 months ago
5.0 - 9.0 years
0 Lacs
karnataka
On-site
As a Physical Design Engineer, you will be responsible for the complex SOC top physical implementation of next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of both complex blocks and full-chip designs. You will be expected to demonstrate expertise in top-level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. A strong understanding of timing, power, and area ...
Posted 4 months ago
7.0 - 12.0 years
32 - 47 Lacs
Bengaluru
Work from Office
Experience place & route flow, hierarchical design,Synthesis, Static Timing Analysis ,7nm, hierarchical designs
Posted 5 months ago
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