10–12 years of experience in business development and sales, specifically in offshore IT staff augmentation International staffing and resource management models Excellent network and connections in the US, UK, or EU IT markets is a strong advantage
Develop and improve existing flow for logical equivalent check Experience with ABORT/NEQ debugging process Hands- on in logical equivalence tools such as Conformal LEC and/or Formality Understanding cross-functional RTL/PD/DFT teams Perl, Python, TCL
PMIC/ 180 nm Block with DC-DC Converter/ Buck Boost Must have strong exp in Power Sequencing/ Voltage Controller exp with LDO/ OPAMP
Lead Verification Efforts, Guide a team of engineers in developing and executing verification plans for complex designs, including PCIe-based IP or SoC. Testbench Development, Protocol Expertise, Methodology and Tools, Coverage Driven Verification
Strong System Verilog and UVM expertise ,DDR protocol knowledge ,GLS experience ,Testbench development, Test planning and execution , debugging & scripting skills
, multi-voltage domain designs., multiple PVT conditions using Tempus. , STA tools - Tempus, cross-talk noise, Signal Integrity, Layout Parasitic Extraction,
Experience place & route flow, hierarchical design,Synthesis, Static Timing Analysis ,7nm, hierarchical designs
Power rail / PDN analysis, Perl, Python, TCL, EM and ESD, multi Power domain / Voltage Area/ Power IR
Along with GF- 28nm tech node is "Experience in Mixed signal and Digital hierarchical SoC Designs. Engineers with complete PnR knowledge, Signoff, timing and PV Experience in Mixed signal and Digital hierarchical SoC Designs.
Strong understanding of DFM/DFT/DFA, PCB stack-up, HDI, back drilling, and high-volume production optimization. EDA tools: Cadence Allegro, Altium Designer, PADS., IPC standards EMI/EMC NOTICE PERIOD -30 DAYS
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