Electronic Design Automation Engineer

As an experienced chip design engineer, you will be responsible for the following key domains: - Power Optimization: Utilize low-power design techniques and methodologies, including expertise in the Unified Power Format (UPF). - Timing Optimization: Demonstrate proficiency in static timing analysis (STA) and implement design constraints using the Synopsys Design Constraints (SDC) format. - Functional Safety Analysis: Apply a deep understanding of functional safety concepts and standards (e.g., ISO 26262), employing analysis techniques such as FMEDA and FTA. - Utilize industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys, Cadence, or Siemens EDA. - Proficiency in hardware description languages (HDLs) such as Verilog and SystemVerilog. - Strong scripting skills in Python and Tcl for tool automation and flow development. - Understanding of chip design and implementation flows, from RTL to GDSII. - Excellent problem-solving, debugging, and analytical skills. - Strong communication and presentation skills, capable of explaining complex technical concepts to diverse audiences. Qualifications Required: - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of hands-on experience in chip design, focusing on RTL design, synthesis, static timing analysis (STA), or power integrity. Please note that this job description does not include any additional details about the company.,