1277 System Verilog Jobs - Page 22

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74911 Responsibilities Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design and data converters. Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs. Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs. Ability to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions. Competent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs. Experienced in producing detailed technical reports and documentation. Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred. Experienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc. Simulation performance and accuracy trade-offs based on design requirements Experienced in Power-aware mixed-signal verification Hands-on verification of sub-45nm CMOS SOC designs Desired Experience and Skills Job Segment: Electrical Engineering, Electrical, Design Engineer, Network, Telecom, Engineering, Technology

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

About the Role Skills: Strong in IP / SoC-level verification Responsibilities Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Experience: 5+ years in Design Verification Required Skills Strong in IP / SoC-level verification Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Availability: Immediate to within 4 weeks

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Job Description: We are looking for a RTL Design Engineer with expertise in SoC and IP-level design and integration. The ideal candidate should have a strong background in RTL coding, architecture-level understanding, and industry-standard quality checks and tools. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog Understand and apply top-level SoC architecture concepts Perform SoC and IP-level integration Implement RTL quality checks including CLP (mandatory), LINT, CDC, RDC, VSI Work on design partitioning (Tilification) Handle IORING, PHYs, GPIOs Collaborate with verification and backend teams Required Skills: RTL coding in Verilog and SystemVerilog IPXACT knowledge Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) UPF and SDC concepts Tools: VC_static, SpyGlass (Lint, CDC, RDC), 0in, Formality, Conformal LEC Scripting: Perl, Python, TCL Nice to Have: Experience with design quality metrics and standards Exposure to physical-aware RTL design

Role & responsibilities Please interested candidate send me cv : galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name SoC NoC Verification Engineer Job No : PROX-14080 Position type: Permanent Total Exp: 7+ years to 15y HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: SoC NoC Verification Engineer with 7+ years of experience This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain test benches using SystemVerilog/UVM. Perform functional, performance, and power verification. Debug and resolve design and verification issues. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications. Client is looking for Network on chip , just look for the NoC verification AMD (Dont Share AMD Profiles) Preferred candidate profile

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Role & responsibilities 7+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering As a member of the Design Verification [ Pre-Silicon DV ] Team for client WCS/SCE BU You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/ UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: 7 to 12 years of experience, mainly in design Experience in Verilog and/or SystemVerilog Working experience of AMD/Xilinx FPGA and Vivado Experience in Video domain (DisplayPort/MIPI) is preferred Candidate shall be working AMD Sattva site, Hyderabad. TekWissen Group is an equal opportunity employer supporting workforce diversity.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Description: Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

SILICON DESIGN ENGINEER 2 THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: 7+yrs of p roficient experience in SoC and IP level RTL verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Knowldgeable on AMBA protocols like APB/AHB/AXI etc Required protocols knowledge like USB, I3C, UFS, QSPI etc Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to ARM & RISCV architecture. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SG Benefits offered are described: AMD benefits at a glance .

MTS GFX Design Role: We are currently seeking a highly skilled design engineer for GFX Design team. Responsibilities: In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 8+ Years of Exp Location: Bangalore, India #LI-NS1 Benefits offered are described: AMD benefits at a glance .

THE ROLE: AMD is looking for a s enior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for S oftware engineering development , and is diligent and passionate about Technology . A successful candidate will need to employ strong knowledge in computer technologies, leadership skills in technical areas, and SW engineering expertise as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators. KEY RESPONSIBILITIES: Develop and drive execution of comprehensive , highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team C ollaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results PREFERRED EXPERIENCE: Strong digital design and simulations basics RTL (VHDL, Verilog & System Verilog) coding skills Understanding of FPGA design flow and tools (Synthesis, Simulation and implementation) ASIC/FPGA verification experience VHDL and Verilog Xilinx Vivado Design Suite experience Hands on experience on simulators like XSIM, Questa, Modelsim, VCS etc. Advanced Debug skills in software environment or strong problem-solving skills Hands on experience with scripting preferably tcl, pearl and python ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer/Software Engineering, Computer Science, or related technical discipline #LI-NR1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER (Timing Constraints/STA Signoff ) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. T HE ROLE : As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure P REFERRED EXPERIENCE : 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology. Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing. Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: SoC RTL Integration Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Primary Responsibilities:- Lead complex SoC integration efforts, including the development of top-level architecture and interconnect fabric Design and implement critical integration components such as clock/power distribution networks, reset controllers, and system-level arbitration Resolve sophisticated interface compatibility issues between IP blocks from various sources Develop and maintain comprehensive integration verification strategies Collaborate with IP teams to ensure seamless integration of all subsystems Perform thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis Drive timing closure at the integration level in coordination with physical design teams Implement and optimize system-level power management schemes Lead design reviews and provide technical guidance to junior integration engineers Develop technical specifications for SoC-level integration requirements Required Technical Skills:- 7+ years of RTL design experience with 4+ years focused on SoC integration Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) Proven experience with large-scale integration challenges in complex SoCs Strong understanding of clock synchronization strategies and metastability management Deep knowledge of power management techniques and implementation Experience with integration-specific verification methodologies Proficiency in debugging complex system-level issues Advanced understanding of timing analysis and constraints at the integration level Advanced Capabilities: Ability to identify and address system-level bottlenecks affecting performance Experience optimizing interconnect architectures for bandwidth and latency requirements Knowledge of security isolation requirements for modern SoCs Skill in balancing conflicting requirements from multiple IP teams Experience mentoring junior engineers on integration methodologies Ability to influence architectural decisions based on integration considerations At the MTS level, you would be expected to independently lead major integration efforts, serve as a technical authority on integration challenges, and contribute to architectural decisions that affect the entire SoC design. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Expertise in block level and system level verification using UVM Proficiency in coding UVM tests Strong debugging skills for resolving failure In-depth experience in coverage analysis and functional coverage Knowledge in scripting

1+ Yrs Experience working on modern front-end web technologies, including: React, JS(ES6+) TypeScript, Next.js, HTML5, CSS3 and Less/Sass ability to write mixins, partials, functions, etc developing highly-optimized applications using React and Redux Required Candidate profile Experience interning in the E-Commerce Experience with the standard tooling Webpack, Babel, Linting, JS Typing, and Prettier. Experience in Caching

We are seeking a highly skilled and experienced DV Lead to drive the verification of complex System-on-Chip (SoC) designs. The ideal candidate will be proficient in SoC-level verification methodologies , have strong expertise in writing C test cases for embedded systems, and lead verification planning and execution for SoC projects. Key Responsibilities: Lead the end-to-end SoC verification lifecycle, from test planning to coverage closure. Define verification strategy , test plans, and verification infrastructure for SoC-level designs. Develop and execute C-based test cases for processor and peripheral verification in a simulation/emulation environment. Collaborate with RTL design, firmware, and software teams to ensure complete SoC-level functional coverage. Drive debugging efforts across multiple functional blocks and coordinate with cross-functional teams to resolve issues. Utilize industry-standard verification tools and methodologies (e.g., UVM, System Verilog, C, scripting). Manage a team of verification engineers and ensure timely delivery of milestones.

Experience: 6 - 15 years Responsibilities: Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in SoC verification using Experienced in one or more of various verification methodologies UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.)

You will work on the verification of a server-class microprocessor-based SOC. you'll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. you'll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Design Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements. The DV Team at Ampere comprises of stellar folks who have dedicated themselves to the art and fun of design verification. We are a tightly-knit, fast-paced team who work extremely closely with our design and architecture partners to ensure no bug is left behind. Define requirements for sub-system level and full-chip level testing infrastructure Create test plans for sub-system and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Hardware verification experience in IPs or SoC on at least 1 product life cycle Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (eg, C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Understanding of ARM, RISCV or x86 assembly language programming is a plus Understanding of CPU architecture, coherent fabrics spanning processor cores, memory, caches and die to die interconnects, coherent protocols like ARM s ACE/CHI is a plus Good written and verbal communication skills, excellent attention to detail, strong analytical/problem solving skills. What we'll offer: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as we'll as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.

We are hiring a ASIC Verification Engineer to help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain specific processors for the IAAS and smart-switch markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and security virtualization services for both the public and private cloud markets. THE ROLE: In this role, you will be responsible for defining test strategies and plans, developing test benches and test cases, and debugging designs helping with micro-architecture. You will participate in design verification methodology definition as we'll as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. Your work and skills will be leveraged across module-level, full chip, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform software. KEY RESPONSIBILITIES: With your solid knowledge and understanding of Computer Architecture you will be: Developing and executing test plans for Unit/IP/Subsystem/ SOC level verification System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills PREFERRED EXPERIENCE: Languages and tools: UVM, System Verilog, C or C++ System Verilog simulators and waveform debuggers Experience developing and executing test plans for Unit/IP/Subsystem/ SOC level verification Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) Solid knowledge and understanding of Computer Architecture Excellent debugging and problem-solving skills ACADEMIC CREDENTIALS: BSEE or equivalent. MSEE preferred