Staff Engineer , Design Verification

Analog Devices

7 - 12 years

25 - 35 Lacs

bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

eda system verilog uvm perl tcl python

Work Mode

Hybrid

Job Type

Full Time

Job Description

SystemVerilog and UVM Expertise
: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs
Test Planning and Strategy
: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure
Mixed-Signal Verification
: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches
Debugging Mastery
: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction
EDA Tool Proficiency
: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques
Scripting and Automation
: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks
Technical Leadership
: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams

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