Responsibilities: * Collaborate with cross-functional teams on ASIC projects from concept to delivery. * Design, code & verify RTL using Verilog/System Verilog, Xilinx FPGAs & VLSI methodologies.
Responsibilities: * Collaborate with cross-functional teams on ASIC projects from concept to delivery. * Design, code & verify RTL using Verilog/System Verilog, Xilinx FPGAs & VLSI methodologies.