Design Verification/GLS

Role Overview: As a Verification Engineer, you will be responsible for reading specifications and developing test plans. You will utilize your strong debugging skills in UVM and System Verilog to create monitors, scoreboards, sequencers, and sequences. Your expertise will be crucial in increasing the efficiency of bug detection and resolution. Key Responsibilities: - Develop test plans based on specifications - Utilize scripts, System Verilog, UVM, UVM_REG, and methodologies to create monitors, scoreboards, sequencers, and sequences - Demonstrate technical expertise in functional verification of complex designs - Develop test benches, generate stimuli, perform checking, and ensure functional coverage Qualifications Required: - Strong debugging skills in UVM and System Verilog - Experience in functional verification of complex designs - Ability to analyze coverage and debug failures effectively Additional Details: The company values individuals who are comfortable with checking builds, navigating large test benches, analyzing coverage, and performing additional debugging. As a Verification Engineer, you will be expected to delve into failures and understand the underlying issues thoroughly.,