1277 System Verilog Jobs - Page 17

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Semiconductor Integration. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Job Title: VLSI Engineer (Academic Role Teaching Computer Architecture) Location: Rishihood University, Sonipat (On-site) Type: Full-Time | Immediate Joiners Preferred Experience: 37 years Department: Engineering & Technology | Academic Instruction About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are builtfrom logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience—covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering , Electronics , Electrical , or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence , ModelSim , Synopsys , Xilinx , Mentor Graphics , etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting ( Tcl , Shell , Python ). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V , ARM-based processors, SoC Design, or low-power systems. Exposure to DFT , verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Why Join Us? Work at the intersection of deep tech and academia in a modern, innovation-led learning environment. Influence curriculum and pedagogy at a forward-thinking institution backed by Newton School of Technology and Rishihood University . Collaborate with a team of industry leaders and passionate educators in building India’s next generation of engineers.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Board Design.

8+ yrs of experience in AMS verification and mixed-signal design, UVM System Verilog (UVM/SV), and C-based compile flow, ARM M-series (Cortex M33, M85, M55, M4, M0 etc) and RISC-V processor, Spectre and Xcelium tools, scripting - Python, Perl

The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route.: Experience: 1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience:Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the >

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification Experience: 3-5 Years

Role & responsibilities To play the role of Verification engineer at the Block level verification. Develop verification test plans from design specifications. Development of test environments using System Verilog and UVM verification methodologies. Integration with RTL and basic simulation bring-up for the design. Create multiple test cases as per test plan and launch regressions. Generate Code/Functional coverage, analyze coverage results and correlate with the test plan. Working the design team members to identify and quickly resolve problems with the design. Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenge Preferred candidate profile Domain Expertise : AHB, AXI, PCIe, USB and Ethernet. Languages (must): Verilog, system Verilog Methodologies (One of them is must): OVM/UVM/VMM EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog Experience in developing Test Bench components in both block level and SOC level. Experience in Creating test plan and Writing test sequence. Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable) Good analytical and problem-solving skills Excellent written and verbal communication in English. Good teamwork and the desire to excel in a competitive environment. Qualification: Bachelor's Level Degree (ECE, EE / preferred specialization) with more than 9 years of work experience

Job Requirements Engineer must possess string understanding od Design Verification with 5+ Year of exp. Engineer must possess strong understanding of SystemVerilog, UVM.

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 12+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

Job Requirements Develop and execute verification plans for SoC-level designs. Build UVM/SystemVerilog-based testbenches integrating multiple IPs. Write and maintain testcases, sequences, assertions, and coverage models. Perform functional, system, and performance verification. Debug simulation failures and collaborate closely with designers and architects. Drive coverage closure and track verification metrics. Support emulation and FPGA prototyping environments as needed. Mentor junior engineers and contribute to process improvements. Required Skills Strong experience in SystemVerilog and UVM methodology. Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols. Hands-on expertise in random constrained stimulus generation and functional coverage. Proficiency in debug tools (SimVision, Verdi, DVE). Experience with simulation tools (VCS, Questa, Incisive). Exposure to gate-level simulations, power-aware verification, and low-power design concepts. Knowledge of scripting (Perl, Python, Tcl). Good to Have Experience in emulation platforms (Palladium, Veloce). Familiarity with formal verification techniques. Knowledge of cache coherency protocols and memory subsystems Education B. E/B. Tech or M. E/M. Tech in Electronics, related field. Work Experience Required Skills Strong experience in SystemVerilog and UVM methodology. Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols. Hands-on expertise in random constrained stimulus generation and functional coverage. Proficiency in debug tools (SimVision, Verdi, DVE). Experience with simulation tools (VCS, Questa, Incisive). Exposure to gate-level simulations, power-aware verification, and low-power design concepts. Knowledge of scripting (Perl, Python, Tcl).

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors. Siemens EDA is a global technology leader in Electronic Design Automation software. Their software tools empower companies worldwide to develop innovative electronic products efficiently. By using these tools, customers are able to advance technology and physics boundaries to deliver superior products in the complex realm of chip, board, and system design. This is your role. Aprisa provides comprehensive functionality for top-level hierarchical design and block-level implementation for intricate digital IC designs. The detail-route-centric architecture and hierarchical database at Aprisa facilitate the acceleration of design closure and attainment of optimal quality results within a driven runtime. Aprisa is currently engaged in developing the next-generation RTL-to-GDSII solution and is seeking individuals to join this pioneering journey. **Role:** - Drive and oversee the design and development of various aspects of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Guide and lead team members towards successful project completion by introducing innovative and effective solutions. - Collaborate with a dedicated team of experts. **Must-Have Requirements:** - Bachelor's or Master's degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Proficient in C/C++, algorithms, and data structures. - Strong problem-solving and analytical skills. - Leadership abilities to inspire and support the team with your expertise. **Great to Have Experience in:** In this role, you will have the opportunity to work with RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Furthermore, you will be involved in designing C or RTL IPs, optimizing RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly appreciated, along with your proficiency in scripting languages like Python and TCL. Join Siemens, a diverse collective of over 377,000 individuals shaping the future in more than 200 countries. Siemens is committed to equality and encourages applications that reflect the diversity of the communities where they operate. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help shape tomorrow!,

Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets, and other product categories. The System Memory Management Unit performs virtual to physical address translation, dynamic allocation, and access control of DDR memory, designed as per ARM SMMU architecture spec. Your job responsibilities will include owning DV test bench and other associated collaterals such as Checkers, Trackers, Scoreboards, Assertion, Functional Coverage. You will develop a test plan and test cases to cover the design feature set, ensuring code coverage and functional coverage closure at different levels of the test bench. Collaborate closely with System Architects, Design, and emulation teams on failure debugs, code/functional coverage closure, regression signature debugging, and bug fixes identification. You will also be responsible for developing/deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) and debugging and root causing post-silicon issues in collaboration with Design, SW, and test teams. Additionally, you will work with SoC performance modeling team on latency and bandwidth analysis. The required skillset for this role includes strong debugging, analytical, and problem-solving skills, expertise in UVM, System Verilog coding, knowledge about ARM bus protocols, Virtual Memory concepts, SoC system architecture, and experience in developing Monitors, Scoreboards, Sequencers utilizing scripts, System Verilog, UVM, and methodologies for efficient bug identification and resolution. Post-si bring-up and HW-SW debug experience would be advantageous. Effective communication and collaboration skills are essential to work with a large world-wide design organization. Desired skillset includes experience in designs optimized for low power - Dynamic clock gating, Logic/Memory power collapse, and proficiency in any of the Scripting languages (Python or Perl). Qualcomm is looking for candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience OR a Master's degree in a relevant field and 2+ years of related work experience OR a PhD and 1+ year of relevant work experience. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, contact Qualcomm at disability-accomodations@qualcomm.com. Qualcomm expects its employees to comply with all applicable policies and procedures, including those related to the protection of confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is for individuals seeking jobs directly with Qualcomm and unsolicited resumes/applications will not be accepted. Contact Qualcomm Careers for more information about this role.,

As an RTL Design Engineer at Google, you will utilize your expertise in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Your role will involve scripting in languages such as Perl or Python, as well as focusing on area, power, and performance optimization. Ideally, you hold a Master's degree or PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Experience in designing and developing security blocks or crypto blocks will be beneficial for this position. Join a diverse team at Google that is dedicated to pushing boundaries and creating custom silicon solutions for the future of direct-to-consumer products. Your contributions will drive innovation behind globally loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes tasks such as Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews, and closure to ensure high-quality and optimized security designs. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our team combines Google AI, Software, and Hardware to create radically helpful experiences, researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power for the betterment of people's lives. Your responsibilities will include participating in test planning and coverage analysis, developing RTL implementations meeting power, performance, and area goals, engaging in synthesis, timing/power closure, FPGA and silicon bring-up, Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, as well as conducting Lint/CDC/FV/UPF checks. Additionally, you will create tools and scripts for task automation and progress tracking.,

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors who are passionate about electronic design automation software. As a global technology leader, Siemens EDA provides innovative tools that empower companies worldwide to develop cutting-edge electronic products efficiently. By utilizing our software solutions, our customers can navigate the complexities of chip, board, and system design while pushing the boundaries of technology and physics to deliver superior products. Your Role: As part of the Aprisa team, you will play a crucial role in the development of top-level hierarchical design and block-level implementation for complex digital IC designs. Leveraging our detail-route-centric architecture and hierarchical database, you will expedite design closure and achieve optimal quality results within a driven runtime. Join us in shaping the next-generation RTL-to-GDSII solution and become an integral part of this innovative journey! Key Responsibilities: - Drive and oversee the design and development of various components of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Provide guidance and leadership to ensure successful project completion through innovative and effective solutions. - Collaborate with a dedicated team of experts to achieve common goals. Requirements: - Hold a B.Tech or M.Tech degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Possess a strong grasp of C/C++, algorithms, and data structures. - Demonstrate exceptional problem-solving and analytical skills. - Lead and motivate the team with your expertise. Desirable Experience: You will have the opportunity to: - Develop RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. - Design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. - Utilize parallel algorithms and job distribution strategies, along with proficiency in scripting languages like Python and TCL. Join Siemens: Siemens is a global community of over 377,000 individuals working together to shape the future across 200 countries. We value diversity and equality, and we welcome applications that represent the various communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help us pioneer tomorrow!,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience:3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience:1-3 Years.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: IP Sub system Verification Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Need verification engineers with solid verification experience(5+ year) at IP subsystem level. Good experience in SV/UVM based testbench creation, test case writing, checkers, monitors, debugs, coverage analysis. IP level verification experience preferred in high speed IOs like DDR/USB/PCIE etc. General expertise in infrastructure, tools like Perl, Python etc. Senior leads should have experience in doing hands-on as well as leadership responsibilities. Expected time for onboarding : Immediate. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Design For Testability - DFT. Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.