You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,
You should have in-depth knowledge of full custom (transistor level) CMOS VLSI circuit layout techniques, with the ability to create high-density, high-performance CMOS layouts and understand tiled layout. You must be familiar with CAD tools for IC layout, design rule checking, and layout vs. schematic comparison (LVS). Experience using Cadence & Mentor digital/analog design tool suite, Simulators - Avant! H SPICE / Mentor ELDO simulator / NASDA HSIM & verification tools like Mentor Calibre & Cadence Dracula is required. Additionally, you should possess knowledge in developing behavioral models for design sub-blocks/digital circuits. The minimum educational requirement for this position is a BS in EE, while an MS in EE is preferred. If you meet these qualifications and are interested in this opportunity, please email your resume to careers@perfectus.com with Job Code DE in the subject line.,
You will be responsible for design verification at chip level to ensure that the design meets architectural and system requirements. This includes developing test environment, test bench, bus protocol checking, transaction level checking, and performance modeling. Experience in advanced verification languages such as VERA, Specman, and System C is desirable. You should have 3-5 years of solid design verification experience. A minimum educational requirement is a BS in EE, while an MS in EE is preferred. If you are interested in this position, please email your resume to careers@perfectus.com with Job Code VE in the subject line.,
As a FPGA Design Engineer at our company, you will be responsible for high-speed multimillion-gate and multi-clock domain FPGA designs. Your role will involve translating hardware requirements into a proven, scalable system architecture and design. From initial specifications to silicon, you will be leading the design process. We are looking for someone with experience in Xilinx / Altera FPGAs, embedded multi-processor interface architectures, Verilog/VHDL RTL design, verification, FPGA synthesis/timing, and lab validation planning/execution. Your educational background should include a BS in EE, while an MS in EE is preferred. If you are interested in this exciting opportunity, please email your resume to careers@perfectus.com with the Job Code FPGA in the subject line. We look forward to reviewing your application.,