500 System Verilog Jobs - Page 13

locationsIndia, Bangalore time typeFull time posted onPosted 17 Days Ago job requisition idJR0274344 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications.Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to micro-architecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.Replicates, root causes, and debugs issues in the pre-silicon environment.Finds and implements corrective measures to resolve failing tests.Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum Qualifications:BS with 10+ years/MS with 8+ years industry experiencesExperience on Pre-Si validation on Emulation, preferably Zebu.Experience on validation at MCP.Experience with pre-Si verification with System Verilog OVM/UVM on content development Scripting languages such as Python, Simics.Good understanding of RTL, Verilog, VHDL.Preferred Qualifications:Experience with Synopsys simulation and coverage tools.Assertion based verificationRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0272648 Job Details: About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 10+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience The years of experience mentioned above must focus on formal verification Preferred Qualifications: Knowledge of GPU Formal verification experience in at least one of these areasArbitration logic, low power design, memory controller, transaction router/bridge. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270512 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 5+ years of industry experience, or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 3+ years of industry experience Years of experience must include at least three of the following skills: Hardware architectures, system level IC design implementation knowledge of how to create end use scenarios IP level or SoC level validation experience Processor-based SoC level verification, in native Verilog, SystemVerilog and UVM mixed environments Verification tools such as VCS, waveform analyzer and/or third-party VIP/BFM integration (e.g. Synopsys VIPs) UVM verification Strong understanding of design concepts and ASIC flow Preferred Qualifications and experience that will make you stand out: Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable Understanding of AXI-AMBA. Protocol variants is desirable Strong technical background in FPGA prototype emulation and debug Proven technical background in silicon validation, failure analysis and debug Validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART Prior hands-on automation script development and optimization using C/C++, Python Good understanding of embedded firmware/software development process Functional knowledge and experience in JTAG Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Looking for below - Architect/Lead ASIC designer/Lead Design verification/Lead Formal Verification/Lead Emulation/Lead Synthesis Engineer/Lead Implementation Engineer/Lead DFT Engineer/Lead Share your updated CV at jatin@smrd.in

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

Key Responsibilities: Ownership of Developing Leads / Client Pipelines from the USA Canada Month-on-Month: Meeting targets End-to-end responsibility for prospect development (Cold calling, LinkedIn, Social Media, Video-Discussions, referrals etc.) Must have hands-on experience and proven successes in Lead Generation for USA Specific to IT Services / Digital Solutions and/or Staffing. MUST own up and deliver impressive client addition targets The position will develop into Front-end sales for USA and Canada, as a Business Development Manager with direct Revenue responsibility and international travels, Relationship Management and Account Mining responsibilities over 2 to 4 years of successful Inside sales performance. Desired Candidate Profile: Should have hands-on experience in lead generation for Digital IT services for the USA market. Ability and experience to get connected at senior management levels of Client Organizations (CEO, CTO, CIO, VP Director levels). Must have good IT/Digital market understanding and connections: Ability to get started quickly Ability to line up discussions for senior management / BD managers Maturity, clarity and experience required with senior connects in organizations from USA Canada Ability and experience of having impressive pitching and positioning at CXO / VP level Must have sound knowledge of Digital Technologies / IT solutions Must have worked in the US region extensively on Digital IT services Candidate must come with high energy enthusiasm and ambitious Good communication skills.

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG / MBIST / Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams. Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG/MBIST/Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.

Mirafra is Hiring! OnsiteOpportunity #JoinUs Location: Any European Location (Germany, Romania Preferred) Notice Period: Immediate to 45 Days Visa : Sponsorship Available (Open to candidates from India) Exp: 7+ yrs We're looking for talented professionals with hands-on experience in Specman and NVM Digital Verification to join our global team. Key Skills: Verification planning and testbench creation Datapath, ECC, FSMs, FPGA models, and full-custom assertions Strong documentation and review presentation abilities Looking for a chance to work abroad and take your career to the next level? This is it! Apply now share your resume at: swarnamanjari@mirafra.com

Design Verification Engineer (4-10 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 4-10 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

Position: ASIC RTL Design Lead (SI90FT RM 3217) Job Description: Innovate, implement, and verify RTL code for complex PHY sub systems dealing with high speed blocks using Verilog/System Verilog knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Previous experience with storage systems, protocols, in NAND flash /DRAM controller PHY Basic understanding of PHY system level concepts Experience in PHY architecture, power management and Registers understanding to interact with FW design. Proficient in C, C++, Lint Excellent interpersonal skills and Team Player High level of integrity and commitment to quality and timeliness. Understanding of Hardware Block Diagrams, Schematics Understanding of PHY Architecture document and programming guidelines Understanding of PHY integration guidelines implementation Strong can-do attitude Job Category: Embedded HW_SW Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-30 days

Position: Design Verification Engineer (SI70FT RM 3214) Basic qualifications Bachelor s/ Master s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 7 Years Notice period: 0-30 days

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do Will be responsible for verification of IP, Block, or Subsystem at Soc Level Generate appropriate documentation for verification Responsible for analyzing/debugging given blocks/tasks in verification Should be able to develop and own the verification environment, verification components developed You will report to Lead Engineer What Youll Need: 5+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification Have worked on IP level or Block level or SoC level functional verification Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology philosophy Expert in System Verilog, Verilog, and OVM/UVM verification methodology Have working experience on AMBA interface protocols (AXI, AHB, APB) Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must Hands-on experience on working one or more of the following protocols is a must - UART, I2C, SPI, QSPI, I3C, eMMC, CAN, Hands-on experience working with one or more of the following protocols is desired - PCIe, USB, DDR, LPDDR, GBE, SATA Experience with Perl, Python or similar scripting languages will be helpful Ability to adapt learn, quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals. We have a flexible work environment to support and help employees thrive in personal and professional capacities As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Position: Design Verification Ethernet MAC (SI80FT RM 3219) Required Skills Experience Ethernet Expertise: Strong understanding of 100G/400G Ethernet architecture. Hands-on experience with MAC, PCS, PMA, Auto-Negotiation, and Link Training. Working knowledge of IEEE 802.3 (100GBASE-KR, 400GBASE-R, etc.). Experience level: 5-10 years. Proficiency in SystemVerilog and UVM methodology. Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 8+ years Notice period: 0-30 days

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Sr Engineer, Digital Design Job Description Design key digital blocks such as clocks, reset paths, memory controller, NVMs etc. in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug Trace, TZC) and their integration requirements Design for Test skills on SCAN, MBIST boundary scan, JTAG and ARM DAP interface and general functional DFT understanding. Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces peripherals ATPG vectors, MBIST and BSCAN post silicon debug support. Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc. Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Staff IP/RTL Design Engineer for TPU Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 5-10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 5-10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Memory ControllerVerification- Principal Location: Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for experienced and talented professional for DDR Memory Controller Verification. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 10+ years of experience or ME/MTech in Electrical/Computer engineering with 8+ years of experience Should have hands on experience in System Verilog, UVM/OVM and Object-Oriented Programming Proven track record in DDR5/LPDDR5X/LPDDR6/HBM4 IP verification from environment and tests development to validation closure Work closely with RTL designers and SOC team to scope out integration and verification requirements Proficiency in bus protocols AXI/AHB Integration and verification of complex System IP features. Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols Knowledge of Fabric/Network on chips, Cache Coherency Experience in GLS is added advantage. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Memory Controller - Staff Verification Engineers Location : Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Staff Verification Engineers: looking for experienced and talented professional for DDR Memory Controller Verification. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 6-8+ years of experience Should have hands on experience in System Verilog, UVM/OVM and Object-Oriented Programming Proven track record in DDR5/LPDDR5X/LPDDR6/HBM4 IP verification from environment and tests development to validation closure Work closely with RTL designers and SOC team to scope out integration and verification requirements Proficiency in bus protocols AXI/AHB Integration and verification of complex System IP features. Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols Knowledge of Fabric/Network on chips, Cache Coherency Experience in GLS is added advantage. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Role Overview: As our Lead, you ll be at the forefront of guiding projects involving cutting-edge mixed-signal circuits, data converters, sub-sampling phase-locked loops, Serdes, and RF circuits. Leveraging your expertise in CMOS and BiCMOS technologies, alongside your proficiency in Cadence custom IC EDA tools, you ll be pivotal in realizing successful layouts. Collaborate closely with cross-functional teams, spanning both local and international domains, to drive project execution and ensure seamless hardware and software system integration. Key Responsibilities: Spearhead the development and coordination of ASICs. Collaborate with vendors and remote teams to ensure timely delivery of ASICs within specified deadlines and budget constraints. Liaise with foundries for Multi-Project Wafer (MPW) release. Conduct thorough evaluation and characterization of ASICs to ensure compliance with the specifications. Requirements: PhD/Master s degrees from esteemed universities. Demonstrated success in leading multiple mixed-signal ICs from concept to production. Over a decade of industrial experience in analog and mixed-signal design. Proven track record of realizing more than 5 ASIC designs. Profound expertise in Cadence custom IC EDA tools. Proficiency in system and behavioralmodeling using MATLAB, System Verilog, Verilog-A/AMS. Desired familiarity with HDL languages Verilog and/or VHDL. Proficient in scripting languages such as Python, Perl, and C; additional skills are a plus. Experience with design, implementation, and development environments for reconfigurable systems, such as FPGAs, is advantageous. Knowledge of silicon manufacturers and various CMOS process technologies is beneficial. Desired Aptitudes: Proficient leadership and management skills, capable of fostering high-performance teams. Strong individual contributor with a collaborative mindset, able to work effectively within teams. Adaptability to diverse customer bases and openness to periodic local and international travel. Aptitude for quickly learning new technologies and applications. Exceptional writing, verbal, and interpersonal communication skills. Competence in developing innovative solutions and effectively identifying problems. Understanding of production processes to ensure quality and robustness.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Place and Route. Experience1-3 Years.