You will work with some of the brightest people you'll ever meet. Engineers, Analysts, and Product owners collaborate to identify, develop, and maintain world-class financial solutions. Your responsibilities will include creating and sourcing a wide variety of designs for implementation and validation on FPGA boards, system-level integration and testing, timing closure of FPGA Designs, and developing methodologies for HW validation for different types of designs. Desired Skills: - A four-year degree in ECE/EEE, VLSI Design, or a related field, or equivalent training/experience - Knowledge in Logic design /RTL coding using Verilog, System Verilog, or VHDL - Hands-on expertise in Multi Clock designs, Asynchronous interfaces - Strong understanding of FPGA design methodology and familiarity with Intel/Xilinx-Vivado tool flow - Proficiency in synthesis, simulation, implementation, and timing analysis - Knowledge of onboard validation and debugging failures of a design - Knowledge of PCIe, DDR, and TCP/IP cores is a plus Note: Fresh graduates (2023 to 2025 pass out) from IIT, NIT, from any branch are preferred.,
You will work with some of the brightest people you'll ever meet. Engineers, Analysts, and Product owners collaborate to identify, develop, and maintain top-notch financial solutions. - Create and source a wide variety of designs that can be implemented and validated on FPGA boards - Conduct system-level integration and testing - Ensure timing closure of FPGA Designs - Develop methodologies for HW validation for different types of designs Desired Skills: - Four-year degree in ECE/EEE, VLSI Design, or related field and/or equivalent training and/or experience - Knowledge in Logic design / RTL coding using Verilog, System Verilog, or VHDL - Hands-on expertise in Multi Clock designs, Asynchronous interfaces - Strong understanding of FPGA design methodology and familiarity with Intel/Xilinx-Vivado tool flow - Proficient in synthesis, simulation, implementation, and timing analysis - Knowledge of onboard validation and debugging failures of a design - Knowledge of PCIe, DDR, and TCP/IP cores is a plus Please note: Freshers graduate (2023 to 2025 pass out) from IIT, NIT, from any branch are preferred.,