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RTL Design Engineer (IP / Subsystem / VHDL / Verilog / AHB-APB)

RTL Design Engineer (IP / Subsystem / VHDL / Verilog / AHB-APB)

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Symphisys

6 - 9 years

8 - 11 Lacs

hyderabad

Posted:1 day ago| Platform:

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Skills Required

soc verification c++ soc vhdl sub-system verilog hdl apb rtl design axi modelsim fpga design rtl coding ahb perl i2c system verilog asic c cdc ip rtl uvm spi verilog vlsi pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are looking for a highly skilled and experienced Quality Assurance Analyst to join our team. The ideal candidate will have 2 to 5 years of experience in quality assurance.

Roles and Responsibility

Develop and implement comprehensive testing strategies to ensure high-quality software products.
Collaborate with cross-functional teams to identify and prioritize testing requirements.
Design, develop, and execute automated tests using various tools and technologies.
Analyze test results, identify defects, and work with development teams to resolve issues.
Develop and maintain detailed documentation of testing processes and procedures.
Participate in continuous improvement initiatives to enhance testing efficiency and effectiveness.

Job Requirements

Strong understanding of quality assurance principles, methodologies, and best practices.
Experience with automated testing tools and technologies such as Selenium, Appium, or TestComplete.
Excellent analytical, problem-solving, and communication skills.
Ability to work effectively in a fast-paced environment and meet deadlines.
Strong attention to detail and ability to identify defects and errors.
Familiarity with version control systems such as Git or SVN.

Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.

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RTL Design Engineer (IP / Subsystem / VHDL / Verilog / AHB-APB)